diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2015-06-06 19:48:25 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-06-08 00:55:07 +0200 |
| commit | 52648623e03e6769ae73ef8ee999d671fb657d62 (patch) | |
| tree | 2e0c7675c40463cb7864b0b119e50eeadf892a78 /src | |
| parent | 4ba3b79537008b4d2448848901212cf2251188d1 (diff) | |
| download | coreboot-52648623e03e6769ae73ef8ee999d671fb657d62.tar.xz | |
Remove empty lines at end of file
Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;
Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
255 files changed, 0 insertions, 273 deletions
diff --git a/src/arch/arm/armv7/exception_asm.S b/src/arch/arm/armv7/exception_asm.S index 1f369bcc05..f54cd85f9f 100644 --- a/src/arch/arm/armv7/exception_asm.S +++ b/src/arch/arm/armv7/exception_asm.S @@ -104,4 +104,3 @@ exception_handler: set_vbar: mcr p15, 0, r0, c12, c0, 0 bx lr - diff --git a/src/arch/arm/armv7/timestamp.c b/src/arch/arm/armv7/timestamp.c index 76e664a183..1b3138f9a8 100644 --- a/src/arch/arm/armv7/timestamp.c +++ b/src/arch/arm/armv7/timestamp.c @@ -26,4 +26,3 @@ uint64_t timestamp_get(void) timer_monotonic_get(×tamp); return (uint64_t)timestamp.microseconds; } - diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c index e02fed30a2..240d924b75 100644 --- a/src/arch/arm/cpu.c +++ b/src/arch/arm/cpu.c @@ -44,4 +44,3 @@ struct cpu_info *cpu_info(void) addr -= sizeof(struct cpu_info); return (void *)addr; } - diff --git a/src/arch/arm64/include/clocks.h b/src/arch/arm64/include/clocks.h index 64e6d0df29..96cdd06adc 100644 --- a/src/arch/arm64/include/clocks.h +++ b/src/arch/arm64/include/clocks.h @@ -40,4 +40,3 @@ enum { CLK_216M = 216000000, CLK_300M = 300000000, }; - diff --git a/src/arch/arm64/timestamp.c b/src/arch/arm64/timestamp.c index cfadf1d7f2..2962c7fe9b 100644 --- a/src/arch/arm64/timestamp.c +++ b/src/arch/arm64/timestamp.c @@ -26,4 +26,3 @@ uint64_t timestamp_get(void) timer_monotonic_get(×tamp); return (uint64_t)timestamp.microseconds; } - diff --git a/src/arch/mips/ashldi3.c b/src/arch/mips/ashldi3.c index 18af6b32e7..de9f738252 100644 --- a/src/arch/mips/ashldi3.c +++ b/src/arch/mips/ashldi3.c @@ -57,4 +57,3 @@ long long __ashldi3(long long u, word_type b) return w.ll; } - diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index 5da91e92f4..d8fd751e3d 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -50,4 +50,3 @@ struct cpuinfo_riscv { struct cpu_info *cpu_info(void); #endif /* __ARCH_CPU_H__ */ - diff --git a/src/arch/riscv/include/arch/header.ld b/src/arch/riscv/include/arch/header.ld index ee4ca427f0..92dec4f1ca 100644 --- a/src/arch/riscv/include/arch/header.ld +++ b/src/arch/riscv/include/arch/header.ld @@ -30,4 +30,3 @@ ENTRY(_start) #else ENTRY(stage_entry) #endif - diff --git a/src/arch/riscv/include/arch/hlt.h b/src/arch/riscv/include/arch/hlt.h index 12099a9b9b..d00302f4df 100644 --- a/src/arch/riscv/include/arch/hlt.h +++ b/src/arch/riscv/include/arch/hlt.h @@ -2,5 +2,3 @@ static inline __attribute__((always_inline)) void hlt(void) { while(1); } - - diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index 3a9b46507c..afe72ec775 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -28,4 +28,3 @@ /* TODO: Need to add DMA_COHERENT region like on ARM? */ #endif /* __ARCH_MEMLAYOUT_H */ - diff --git a/src/arch/riscv/prologue.inc b/src/arch/riscv/prologue.inc index 995ec4631b..517a2854c7 100644 --- a/src/arch/riscv/prologue.inc +++ b/src/arch/riscv/prologue.inc @@ -19,4 +19,3 @@ .section ".rom.data", "a", @progbits .section ".rom.text", "ax", @progbits - diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S index 3fe521ccba..a614b55f03 100644 --- a/src/arch/x86/boot/wakeup.S +++ b/src/arch/x86/boot/wakeup.S @@ -92,4 +92,3 @@ __wakeup_segment = RELOCATED(.) .globl __wakeup_size __wakeup_size: .long . - __wakeup - diff --git a/src/arch/x86/init/crt0_romcc_epilogue.inc b/src/arch/x86/init/crt0_romcc_epilogue.inc index 791ab8e36a..ff93adbc70 100644 --- a/src/arch/x86/init/crt0_romcc_epilogue.inc +++ b/src/arch/x86/init/crt0_romcc_epilogue.inc @@ -19,4 +19,3 @@ __main: post_code(POST_DEAD_CODE) hlt jmp .Lhlt - diff --git a/src/arch/x86/init/prologue.inc b/src/arch/x86/init/prologue.inc index e6645bad21..e0100b5127 100644 --- a/src/arch/x86/init/prologue.inc +++ b/src/arch/x86/init/prologue.inc @@ -21,4 +21,3 @@ .section ".rom.data", "a", @progbits .section ".rom.text", "ax", @progbits - diff --git a/src/arch/x86/lib/timestamp.c b/src/arch/x86/lib/timestamp.c index ae5336c6b7..9df505a570 100644 --- a/src/arch/x86/lib/timestamp.c +++ b/src/arch/x86/lib/timestamp.c @@ -24,4 +24,3 @@ uint64_t timestamp_get(void) { return rdtscll(); } - diff --git a/src/cpu/amd/model_fxx/microcode_rev_c.h b/src/cpu/amd/model_fxx/microcode_rev_c.h index 980572439f..5385ea7e66 100644 --- a/src/cpu/amd/model_fxx/microcode_rev_c.h +++ b/src/cpu/amd/model_fxx/microcode_rev_c.h @@ -145,5 +145,3 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - - diff --git a/src/cpu/amd/model_fxx/microcode_rev_d.h b/src/cpu/amd/model_fxx/microcode_rev_d.h index 61a510c2b2..aee12e20f1 100644 --- a/src/cpu/amd/model_fxx/microcode_rev_d.h +++ b/src/cpu/amd/model_fxx/microcode_rev_d.h @@ -144,5 +144,3 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - - diff --git a/src/cpu/amd/model_fxx/microcode_rev_e.h b/src/cpu/amd/model_fxx/microcode_rev_e.h index 7cdeed0016..568a936d94 100644 --- a/src/cpu/amd/model_fxx/microcode_rev_e.h +++ b/src/cpu/amd/model_fxx/microcode_rev_e.h @@ -145,5 +145,3 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - - diff --git a/src/cpu/amd/pi/00630F01/acpi/cpu.asl b/src/cpu/amd/pi/00630F01/acpi/cpu.asl index 9eb5457377..ed1c975398 100644 --- a/src/cpu/amd/pi/00630F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00630F01/acpi/cpu.asl @@ -108,4 +108,3 @@ ) { } } /* End _PR scope */ - diff --git a/src/cpu/amd/pi/00730F01/acpi/cpu.asl b/src/cpu/amd/pi/00730F01/acpi/cpu.asl index 3b733ddeed..a3bf8f5718 100644 --- a/src/cpu/amd/pi/00730F01/acpi/cpu.asl +++ b/src/cpu/amd/pi/00730F01/acpi/cpu.asl @@ -80,4 +80,3 @@ ) { } } /* End _PR scope */ - diff --git a/src/cpu/amd/socket_939/Kconfig b/src/cpu/amd/socket_939/Kconfig index 6217072e72..6a8c1bf73d 100644 --- a/src/cpu/amd/socket_939/Kconfig +++ b/src/cpu/amd/socket_939/Kconfig @@ -2,4 +2,3 @@ config CPU_AMD_SOCKET_939 bool select CPU_AMD_MODEL_FXX select X86_AMD_FIXED_MTRRS - diff --git a/src/cpu/amd/socket_AM2/Kconfig b/src/cpu/amd/socket_AM2/Kconfig index 7da5a4d210..b0ee3eaa56 100644 --- a/src/cpu/amd/socket_AM2/Kconfig +++ b/src/cpu/amd/socket_AM2/Kconfig @@ -10,4 +10,3 @@ config CPU_SOCKET_TYPE hex default 0x11 depends on CPU_AMD_SOCKET_AM2 - diff --git a/src/cpu/amd/socket_F/Kconfig b/src/cpu/amd/socket_F/Kconfig index 6c2fafa5b5..304aab8a92 100644 --- a/src/cpu/amd/socket_F/Kconfig +++ b/src/cpu/amd/socket_F/Kconfig @@ -9,4 +9,3 @@ config CPU_SOCKET_TYPE hex default 0x10 depends on CPU_AMD_SOCKET_F - diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 7ada0dd267..1d8ea8d844 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -368,4 +368,3 @@ __main: post_code(POST_DEAD_CODE) hlt jmp .Lhlt - diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 49c7746b9a..29d7113600 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -450,4 +450,3 @@ mtrr_table: .word 0x208, 0x209, 0x20A, 0x20B .word 0x20C, 0x20D, 0x20E, 0x20F mtrr_table_end: - diff --git a/src/cpu/intel/fit/Kconfig b/src/cpu/intel/fit/Kconfig index 9b57556827..e48dca9f70 100644 --- a/src/cpu/intel/fit/Kconfig +++ b/src/cpu/intel/fit/Kconfig @@ -9,4 +9,3 @@ config CPU_INTEL_NUM_FIT_ENTRIES depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE help This option selects the number of empty entries in the FIT table. - diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 0266aa81ea..595b4df8b1 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -318,4 +318,3 @@ mtrr_table: .word 0x20C, 0x20D, 0x20E, 0x20F .word 0x210, 0x211, 0x212, 0x213 mtrr_table_end: - diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index ab291abea9..62f816acfd 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -293,4 +293,3 @@ mtrr_table: .word 0x26B, 0x26C, 0x26D .word 0x26E, 0x26F mtrr_table_end: - diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index f2754c52d0..f54c691b9a 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -332,4 +332,3 @@ mtrr_table: .word 0x20C, 0x20D, 0x20E, 0x20F .word 0x210, 0x211, 0x212, 0x213 mtrr_table_end: - diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index d58d1325c8..d7d932e817 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -244,4 +244,3 @@ mtrr_table: .word 0x208, 0x209, 0x20A, 0x20B .word 0x20C, 0x20D, 0x20E, 0x20F mtrr_table_end: - diff --git a/src/cpu/intel/slot_2/Kconfig b/src/cpu/intel/slot_2/Kconfig index 18a5b276d2..436230b964 100644 --- a/src/cpu/intel/slot_2/Kconfig +++ b/src/cpu/intel/slot_2/Kconfig @@ -24,4 +24,3 @@ config DCACHE_RAM_SIZE hex default 0x01000 depends on CPU_INTEL_SLOT_2 - diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig index 38230af5a0..9c3ba56f56 100644 --- a/src/cpu/intel/socket_PGA370/Kconfig +++ b/src/cpu/intel/socket_PGA370/Kconfig @@ -39,4 +39,3 @@ config DCACHE_RAM_SIZE default 0x01000 endif - diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 0d4d45f872..d5d668a202 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -29,4 +29,3 @@ config DCACHE_RAM_SIZE default 0x4000 endif # CPU_INTEL_SOCKET_MPGA604 - diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/cpu/ti/am335x/memlayout.ld index 8a122bcfbb..7947fa25ce 100644 --- a/src/cpu/ti/am335x/memlayout.ld +++ b/src/cpu/ti/am335x/memlayout.ld @@ -39,4 +39,3 @@ SECTIONS } #endif } - diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 20b228ede4..e8a4ee2d3a 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -275,4 +275,3 @@ __main: post_code(POST_DEAD_CODE) hlt jmp .Lhlt - diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index c82edfd936..4dad1e5a7b 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -138,4 +138,3 @@ nullidt: .globl _estart _estart: .code32 - diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index f74e1b8737..b016f8eb16 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -63,4 +63,3 @@ __protected_start: /* Restore the BIST value to %eax */ movl %ebp, %eax - diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index cd8d265ec2..5fbec286a5 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -145,4 +145,3 @@ smm_trampoline32: /* Exit from SM mode. */ rsm - diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 99040758ba..7b70ce9585 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -207,4 +207,3 @@ jumptable: /* core 0 */ ljmp $0xa000, $SMM_HANDLER_OFFSET .align 1024, 0x00 - diff --git a/src/cpu/x86/sse_enable.inc b/src/cpu/x86/sse_enable.inc index 01fce74fe0..ef358ca568 100644 --- a/src/cpu/x86/sse_enable.inc +++ b/src/cpu/x86/sse_enable.inc @@ -27,4 +27,3 @@ /* Restore BIST. */ movl %ebp, %eax - diff --git a/src/device/oprom/x86emu/LICENSE b/src/device/oprom/x86emu/LICENSE index a3ede4a87d..f13d4188ac 100644 --- a/src/device/oprom/x86emu/LICENSE +++ b/src/device/oprom/x86emu/LICENSE @@ -14,4 +14,3 @@ know. Your code will be removed to comply with your wishes. If you have any questions about this, please send email to x86emu@linuxlabs.com or KendallB@scitechsoft.com for clarification. - diff --git a/src/drivers/emulation/Kconfig b/src/drivers/emulation/Kconfig index 3da9f3820c..df8d4ff001 100644 --- a/src/drivers/emulation/Kconfig +++ b/src/drivers/emulation/Kconfig @@ -1,2 +1 @@ source src/drivers/emulation/qemu/Kconfig - diff --git a/src/drivers/i2c/tpm/Kconfig b/src/drivers/i2c/tpm/Kconfig index 5b80079de8..f2b969f5bb 100644 --- a/src/drivers/i2c/tpm/Kconfig +++ b/src/drivers/i2c/tpm/Kconfig @@ -11,4 +11,3 @@ config DRIVER_TPM_I2C_ADDR hex "I2C TPM chip address" default 2 # FIXME, workaround for Kconfig BS depends on I2C_TPM - diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc index 941da3bdf9..cdbda54a8b 100644 --- a/src/drivers/intel/fsp1_0/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc @@ -174,4 +174,3 @@ CAR_init_params: CAR_init_stack: .long CAR_init_done .long CAR_init_params - diff --git a/src/drivers/intel/gma/int15.h b/src/drivers/intel/gma/int15.h index b5abc94fb9..db83f6a3cd 100644 --- a/src/drivers/intel/gma/int15.h +++ b/src/drivers/intel/gma/int15.h @@ -32,4 +32,3 @@ void install_intel_vga_int15_handler(int active_lfp, int pfit, int display, int #else static inline void install_intel_vga_int15_handler(int active_lfp, int pfit, int display, int panel_type) {} #endif - diff --git a/src/drivers/trident/Kconfig b/src/drivers/trident/Kconfig index 691891deab..1dcd5f3382 100644 --- a/src/drivers/trident/Kconfig +++ b/src/drivers/trident/Kconfig @@ -1,2 +1 @@ source src/drivers/trident/blade3d/Kconfig - diff --git a/src/drivers/xgi/common/vb_init.h b/src/drivers/xgi/common/vb_init.h index ef868488d1..cc4ede758f 100644 --- a/src/drivers/xgi/common/vb_init.h +++ b/src/drivers/xgi/common/vb_init.h @@ -22,4 +22,3 @@ extern unsigned char XGIInitNew(struct pci_dev *pdev); extern void XGIRegInit(struct vb_device_info *, unsigned long); #endif - diff --git a/src/drivers/xgi/common/vb_util.h b/src/drivers/xgi/common/vb_util.h index a0806a0525..77c986f2e6 100644 --- a/src/drivers/xgi/common/vb_util.h +++ b/src/drivers/xgi/common/vb_util.h @@ -25,4 +25,3 @@ extern void xgifb_reg_or(unsigned long, u8, unsigned); extern void xgifb_reg_and(unsigned long, u8, unsigned); extern void xgifb_reg_and_or(unsigned long, u8, unsigned, unsigned); #endif - diff --git a/src/drivers/xgi/common/vgatypes.h b/src/drivers/xgi/common/vgatypes.h index 66cf8ea134..2019d54fbb 100644 --- a/src/drivers/xgi/common/vgatypes.h +++ b/src/drivers/xgi/common/vgatypes.h @@ -61,4 +61,3 @@ struct xgi_hw_device_info { /* Additional IOCTL for communication xgifb <> X driver */ /* If changing this, xgifb.h must also be changed (for xgifb) */ #endif - diff --git a/src/drivers/xgi/common/vstruct.h b/src/drivers/xgi/common/vstruct.h index 36d9aa2e81..b4f0939c6b 100644 --- a/src/drivers/xgi/common/vstruct.h +++ b/src/drivers/xgi/common/vstruct.h @@ -548,4 +548,3 @@ struct SiS_Private }; #endif - diff --git a/src/include/cpu/amd/microcode.h b/src/include/cpu/amd/microcode.h index 5ac04e918c..8ebe675f3e 100644 --- a/src/include/cpu/amd/microcode.h +++ b/src/include/cpu/amd/microcode.h @@ -5,4 +5,3 @@ void update_microcode(u32 cpu_deviceid); void amd_update_microcode_from_cbfs(u32 equivalent_processor_rev_id); #endif /* CPU_AMD_MICROCODE_H */ - diff --git a/src/include/cpu/x86/name.h b/src/include/cpu/x86/name.h index e58adb6bec..80b8ea806a 100644 --- a/src/include/cpu/x86/name.h +++ b/src/include/cpu/x86/name.h @@ -23,4 +23,3 @@ void fill_processor_name(char *processor_name); #endif - diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h index 3b0050bba4..6ade04c362 100644 --- a/src/include/romstage_handoff.h +++ b/src/include/romstage_handoff.h @@ -62,4 +62,3 @@ static inline struct romstage_handoff *romstage_handoff_find_or_add(void) } #endif /* ROMSTAGE_HANDOFF_H */ - diff --git a/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb b/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb index 221b80ce68..f1f36938c7 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb +++ b/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb @@ -71,4 +71,3 @@ chip northbridge/amd/lx end end end - diff --git a/src/mainboard/amd/db800/devicetree.cb b/src/mainboard/amd/db800/devicetree.cb index 3331a12ee5..781beb59d8 100644 --- a/src/mainboard/amd/db800/devicetree.cb +++ b/src/mainboard/amd/db800/devicetree.cb @@ -65,4 +65,3 @@ chip northbridge/amd/lx end end end - diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb index 8dd971eef2..898537b155 100644 --- a/src/mainboard/amd/dbm690t/devicetree.cb +++ b/src/mainboard/amd/dbm690t/devicetree.cb @@ -119,4 +119,3 @@ chip northbridge/amd/amdk8/root_complex end #northbridge/amd/amdk8 end #domain end #northbridge/amd/amdk8/root_complex - diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index 1f4e891ebc..c55a8a0290 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -476,4 +476,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb index 9cc4cf78c4..f895d013e5 100644 --- a/src/mainboard/amd/dinar/devicetree.cb +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -106,4 +106,3 @@ chip northbridge/amd/agesa/family15/root_complex end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family15/root_complex - diff --git a/src/mainboard/amd/inagua/Kconfig b/src/mainboard/amd/inagua/Kconfig index c79a0b33f8..d2bf5d0f84 100644 --- a/src/mainboard/amd/inagua/Kconfig +++ b/src/mainboard/amd/inagua/Kconfig @@ -80,4 +80,3 @@ config SB800_AHCI_ROM default n endif # BOARD_AMD_INAGUA - diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 95ee913cc9..9dfc3c7f62 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -392,4 +392,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index 57eabd966f..619d004ea1 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -94,4 +94,3 @@ chip northbridge/amd/agesa/family14/root_complex end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex - diff --git a/src/mainboard/amd/lamar/acpi/si.asl b/src/mainboard/amd/lamar/acpi/si.asl index 9520d581fd..de94071dfd 100644 --- a/src/mainboard/amd/lamar/acpi/si.asl +++ b/src/mainboard/amd/lamar/acpi/si.asl @@ -24,5 +24,3 @@ /* DBGO("\n") */ } } /* End Scope SI */ - - diff --git a/src/mainboard/amd/norwich/devicetree.cb b/src/mainboard/amd/norwich/devicetree.cb index 93effaa717..9a0121d8c1 100644 --- a/src/mainboard/amd/norwich/devicetree.cb +++ b/src/mainboard/amd/norwich/devicetree.cb @@ -38,4 +38,3 @@ chip northbridge/amd/lx end end end - diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 4fe1b4813a..fefac7e7ed 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -454,4 +454,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/amd/olivehillplus/acpi/usb_oc.asl b/src/mainboard/amd/olivehillplus/acpi/usb_oc.asl index b776d68cd1..3d90ba7ddf 100644 --- a/src/mainboard/amd/olivehillplus/acpi/usb_oc.asl +++ b/src/mainboard/amd/olivehillplus/acpi/usb_oc.asl @@ -38,4 +38,3 @@ Name(UOM6, 6) Name(UOM7, 2) Name(UOM8, 6) Name(UOM9, 6) - diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 2e654a77da..09629dd0b8 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -447,4 +447,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 93cfa8d7f2..244ab31243 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -392,4 +392,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/amd/pistachio/acpi_tables.c b/src/mainboard/amd/pistachio/acpi_tables.c index 0ef181d3e5..628abfd192 100644 --- a/src/mainboard/amd/pistachio/acpi_tables.c +++ b/src/mainboard/amd/pistachio/acpi_tables.c @@ -56,4 +56,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb index 760e5abb00..805df7cb41 100644 --- a/src/mainboard/amd/pistachio/devicetree.cb +++ b/src/mainboard/amd/pistachio/devicetree.cb @@ -78,4 +78,3 @@ chip northbridge/amd/amdk8/root_complex end #northbridge/amd/amdk8 end #domain end #northbridge/amd/amdk8/root_complex - diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb index a7a352f8f7..62fb28735e 100644 --- a/src/mainboard/amd/rumba/devicetree.cb +++ b/src/mainboard/amd/rumba/devicetree.cb @@ -18,4 +18,3 @@ chip northbridge/amd/gx2 end end end - diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb index 28b7e01ac6..8ff0e3effe 100644 --- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb @@ -145,5 +145,3 @@ chip northbridge/amd/amdk8/root_complex end #domain end - - diff --git a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt index 5d2755425e..b999dfacbf 100644 --- a/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt +++ b/src/mainboard/amd/serengeti_cheetah/readme_acpi.txt @@ -27,4 +27,3 @@ use c to delele hex file yhlu 09/18/2005 - diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb index 8b5d817708..54c34f8bec 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb @@ -135,5 +135,3 @@ chip northbridge/amd/amdfam10/root_complex # end #domain end - - diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h index b152b047fb..fc2dcafd30 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.h @@ -1,2 +1 @@ unsigned long mainboard_write_acpi_tables(device_t device, unsigned long start, acpi_rsdp_t *rsdp); - diff --git a/src/mainboard/amd/south_station/Kconfig b/src/mainboard/amd/south_station/Kconfig index 53386c57a8..1d3348d427 100644 --- a/src/mainboard/amd/south_station/Kconfig +++ b/src/mainboard/amd/south_station/Kconfig @@ -73,4 +73,3 @@ config VGA_BIOS_ID default "1002,9806" endif # BOARD_AMD_SOUTHSTATION - diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index 716030cad0..d2882a750f 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -392,4 +392,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb index 0a3532fb55..76bedfb44f 100644 --- a/src/mainboard/amd/south_station/devicetree.cb +++ b/src/mainboard/amd/south_station/devicetree.cb @@ -109,4 +109,3 @@ chip northbridge/amd/agesa/family14/root_complex end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex - diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 4499840ff9..af22e65fee 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -447,4 +447,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index 08fcb4d088..09067861ac 100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c @@ -318,4 +318,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/amd/torpedo/devicetree.cb b/src/mainboard/amd/torpedo/devicetree.cb index 8fe9e53f3c..c46d1800aa 100644 --- a/src/mainboard/amd/torpedo/devicetree.cb +++ b/src/mainboard/amd/torpedo/devicetree.cb @@ -87,4 +87,3 @@ chip northbridge/amd/agesa/family12/root_complex end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family12/root_complex - diff --git a/src/mainboard/amd/union_station/Kconfig b/src/mainboard/amd/union_station/Kconfig index ea69fc46a0..4a4a632254 100644 --- a/src/mainboard/amd/union_station/Kconfig +++ b/src/mainboard/amd/union_station/Kconfig @@ -72,4 +72,3 @@ config VGA_BIOS_ID default "1002,9802" endif # BOARD_AMD_UNIONSTATION - diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index 716030cad0..d2882a750f 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -392,4 +392,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb index 0124b17c65..bf98359db5 100644 --- a/src/mainboard/amd/union_station/devicetree.cb +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -85,4 +85,3 @@ chip northbridge/amd/agesa/family14/root_complex end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex - diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 5bb8a37851..1dd42c1543 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -134,5 +134,3 @@ enumerations checksums checksum 392 983 984 - - diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index ef914ec5ca..3829b1da41 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -94,4 +94,3 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, .final = mainboard_final, }; - diff --git a/src/mainboard/arima/hdama/devicetree.cb b/src/mainboard/arima/hdama/devicetree.cb index 2035117101..5bb966d212 100644 --- a/src/mainboard/arima/hdama/devicetree.cb +++ b/src/mainboard/arima/hdama/devicetree.cb @@ -183,4 +183,3 @@ chip northbridge/amd/amdk8/root_complex end # chip northbridge/amd/amdk8 end end - diff --git a/src/mainboard/artecgroup/dbe61/devicetree.cb b/src/mainboard/artecgroup/dbe61/devicetree.cb index d270f3d793..2532885f28 100644 --- a/src/mainboard/artecgroup/dbe61/devicetree.cb +++ b/src/mainboard/artecgroup/dbe61/devicetree.cb @@ -39,4 +39,3 @@ chip northbridge/amd/lx end end - diff --git a/src/mainboard/asrock/939a785gmh/devicetree.cb b/src/mainboard/asrock/939a785gmh/devicetree.cb index f246dcfb31..8b40b9f6d4 100644 --- a/src/mainboard/asrock/939a785gmh/devicetree.cb +++ b/src/mainboard/asrock/939a785gmh/devicetree.cb @@ -129,4 +129,3 @@ chip northbridge/amd/amdk8/root_complex end #northbridge/amd/amdk8 end #domain end #northbridge/amd/amdk8/root_complex - diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index feba7ed59d..ff3e8f4bd5 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -66,4 +66,3 @@ config VGA_BIOS_ID default "1002,9802" endif # BOARD_ASROCK_E350M1 - diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index f8463c4988..2c6eb3b44d 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -392,4 +392,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 1f0b94d781..219b524a57 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -454,4 +454,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 7d81353d9e..b812cd5163 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -446,4 +446,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ PSO_END }; - diff --git a/src/mainboard/asus/f2a85-m_le/buildOpts.c b/src/mainboard/asus/f2a85-m_le/buildOpts.c index 1baa01f4c5..145fb67dcb 100644 --- a/src/mainboard/asus/f2a85-m_le/buildOpts.c +++ b/src/mainboard/asus/f2a85-m_le/buildOpts.c @@ -447,4 +447,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ PSO_END }; - diff --git a/src/mainboard/asus/mew-vm/devicetree.cb b/src/mainboard/asus/mew-vm/devicetree.cb index e0cc9e39eb..397b9993d0 100644 --- a/src/mainboard/asus/mew-vm/devicetree.cb +++ b/src/mainboard/asus/mew-vm/devicetree.cb @@ -49,4 +49,3 @@ chip northbridge/intel/i82810 chip cpu/intel/socket_PGA370 end end - diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index ab9a18a6b2..c7bdab8ce0 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -463,4 +463,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/biostar/am1ml/acpi/sata.asl b/src/mainboard/biostar/am1ml/acpi/sata.asl index 6f4d6d47b1..30733c8cfb 100644 --- a/src/mainboard/biostar/am1ml/acpi/sata.asl +++ b/src/mainboard/biostar/am1ml/acpi/sata.asl @@ -146,4 +146,3 @@ Scope(\_GPE) { } } } - diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 422a8caef2..822eeb2ea2 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -454,4 +454,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb index 9de4331f36..3e02a19a8f 100644 --- a/src/mainboard/broadcom/blast/devicetree.cb +++ b/src/mainboard/broadcom/blast/devicetree.cb @@ -120,4 +120,3 @@ chip northbridge/amd/amdk8/root_complex end #domain end - diff --git a/src/mainboard/cubietech/cubieboard/board_info.txt b/src/mainboard/cubietech/cubieboard/board_info.txt index 14a3755793..c67b641a94 100644 --- a/src/mainboard/cubietech/cubieboard/board_info.txt +++ b/src/mainboard/cubietech/cubieboard/board_info.txt @@ -1,2 +1 @@ Category: sbc - diff --git a/src/mainboard/cubietech/cubieboard/memlayout.ld b/src/mainboard/cubietech/cubieboard/memlayout.ld index 9032ce7d61..6fc798a3ac 100644 --- a/src/mainboard/cubietech/cubieboard/memlayout.ld +++ b/src/mainboard/cubietech/cubieboard/memlayout.ld @@ -33,4 +33,3 @@ SECTIONS RAMSTAGE(0x40000000, 16M) ROMSTAGE(0x41000000, 108K) } - diff --git a/src/mainboard/digitallogic/msm800sev/devicetree.cb b/src/mainboard/digitallogic/msm800sev/devicetree.cb index 839b767931..db511e50ab 100644 --- a/src/mainboard/digitallogic/msm800sev/devicetree.cb +++ b/src/mainboard/digitallogic/msm800sev/devicetree.cb @@ -83,4 +83,3 @@ chip northbridge/amd/lx end end - diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc index 28bf43c91c..2e560d9416 100644 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc @@ -70,4 +70,3 @@ __main: post_code(POST_DEAD_CODE) hlt jmp .Lhlt - diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 8387809996..8801f3520b 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -30,4 +30,3 @@ SECTIONS PRERAM_CBMEM_CONSOLE(0x80000, 8K) RAMSTAGE(0x100000, 16M) } - diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl index 779b6d2be5..1f661cecf2 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/platform.asl @@ -32,4 +32,3 @@ Method(_WAK,1) { Return(Package(){0,0}) } - diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl index 12a716ceef..0706429afd 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi/superio.asl @@ -21,4 +21,3 @@ #define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard #define SIO_ENABLE_PS2M // Enable PS/2 Mouse - diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index 5cda889c89..bcd8870d0f 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -405,4 +405,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index ab9a18a6b2..c7bdab8ce0 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -463,4 +463,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/google/cosmos/chromeos.c b/src/mainboard/google/cosmos/chromeos.c index 75c5efc6cf..e287453d2d 100644 --- a/src/mainboard/google/cosmos/chromeos.c +++ b/src/mainboard/google/cosmos/chromeos.c @@ -38,4 +38,3 @@ int get_write_protect_state(void) { return 0; } - diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c index 3f5adea811..071aaccacb 100644 --- a/src/mainboard/google/link/acpi_tables.c +++ b/src/mainboard/google/link/acpi_tables.c @@ -74,4 +74,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) // the lid is open by default. gnvs->lids = 1; } - diff --git a/src/mainboard/google/nyan_big/bct/spi.cfg b/src/mainboard/google/nyan_big/bct/spi.cfg index e9f85d52c6..c84fe81908 100644 --- a/src/mainboard/google/nyan_big/bct/spi.cfg +++ b/src/mainboard/google/nyan_big/bct/spi.cfg @@ -31,4 +31,3 @@ DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; DeviceParam[3].SpiFlashParams.ClockDivider = 0x16; DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0; - diff --git a/src/mainboard/google/nyan_blaze/bct/spi.cfg b/src/mainboard/google/nyan_blaze/bct/spi.cfg index e9f85d52c6..c84fe81908 100644 --- a/src/mainboard/google/nyan_blaze/bct/spi.cfg +++ b/src/mainboard/google/nyan_blaze/bct/spi.cfg @@ -31,4 +31,3 @@ DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; DeviceParam[3].SpiFlashParams.ClockDivider = 0x16; DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0; - diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index 14d5420aa9..0132e33fff 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -66,4 +66,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) // the lid is open by default. gnvs->lids = 1; } - diff --git a/src/mainboard/google/peppy/i915io.c b/src/mainboard/google/peppy/i915io.c index 1fbdc24af0..eb7b136be2 100644 --- a/src/mainboard/google/peppy/i915io.c +++ b/src/mainboard/google/peppy/i915io.c @@ -141,4 +141,3 @@ void runio(struct intel_dp *dp, int verbose) gtt_write(DEIIR,0x00000000); } - diff --git a/src/mainboard/google/purin/chromeos.c b/src/mainboard/google/purin/chromeos.c index 908a602254..dfe4bba8df 100644 --- a/src/mainboard/google/purin/chromeos.c +++ b/src/mainboard/google/purin/chromeos.c @@ -38,4 +38,3 @@ int get_write_protect_state(void) { return 0; } - diff --git a/src/mainboard/google/storm/mmu.h b/src/mainboard/google/storm/mmu.h index f743d64a8e..956553d2c3 100644 --- a/src/mainboard/google/storm/mmu.h +++ b/src/mainboard/google/storm/mmu.h @@ -22,4 +22,3 @@ enum dram_state { void setup_dram_mappings(enum dram_state dram); void setup_mmu(enum dram_state); - diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 4fa736fc8a..587e1892d9 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -72,4 +72,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* XHCI Mode */ gnvs->xhci = XHCI_MODE; } - diff --git a/src/mainboard/google/urara/boardid.c b/src/mainboard/google/urara/boardid.c index 1d211025fd..564fd4b9f5 100644 --- a/src/mainboard/google/urara/boardid.c +++ b/src/mainboard/google/urara/boardid.c @@ -100,4 +100,3 @@ uint8_t board_id(void) return cached_board_id; } - diff --git a/src/mainboard/google/veyron_brain/chromeos.c b/src/mainboard/google/veyron_brain/chromeos.c index 20e679b67e..7eed42e14b 100644 --- a/src/mainboard/google/veyron_brain/chromeos.c +++ b/src/mainboard/google/veyron_brain/chromeos.c @@ -100,4 +100,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } - diff --git a/src/mainboard/google/veyron_danger/chromeos.c b/src/mainboard/google/veyron_danger/chromeos.c index 20e679b67e..7eed42e14b 100644 --- a/src/mainboard/google/veyron_danger/chromeos.c +++ b/src/mainboard/google/veyron_danger/chromeos.c @@ -100,4 +100,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } - diff --git a/src/mainboard/google/veyron_jerry/chromeos.c b/src/mainboard/google/veyron_jerry/chromeos.c index 0ab77de318..54896391a8 100644 --- a/src/mainboard/google/veyron_jerry/chromeos.c +++ b/src/mainboard/google/veyron_jerry/chromeos.c @@ -146,4 +146,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } - diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index 20e679b67e..7eed42e14b 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -100,4 +100,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } - diff --git a/src/mainboard/google/veyron_mighty/chromeos.c b/src/mainboard/google/veyron_mighty/chromeos.c index 0ab77de318..54896391a8 100644 --- a/src/mainboard/google/veyron_mighty/chromeos.c +++ b/src/mainboard/google/veyron_mighty/chromeos.c @@ -146,4 +146,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } - diff --git a/src/mainboard/google/veyron_pinky/chromeos.c b/src/mainboard/google/veyron_pinky/chromeos.c index 5b44eb3d5c..5e81dad89d 100644 --- a/src/mainboard/google/veyron_pinky/chromeos.c +++ b/src/mainboard/google/veyron_pinky/chromeos.c @@ -147,4 +147,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } - diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index 076b60445d..267c9359bc 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -111,4 +111,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } - diff --git a/src/mainboard/google/veyron_romy/chromeos.c b/src/mainboard/google/veyron_romy/chromeos.c index 20e679b67e..7eed42e14b 100644 --- a/src/mainboard/google/veyron_romy/chromeos.c +++ b/src/mainboard/google/veyron_romy/chromeos.c @@ -100,4 +100,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } - diff --git a/src/mainboard/google/veyron_speedy/chromeos.c b/src/mainboard/google/veyron_speedy/chromeos.c index 0ab77de318..54896391a8 100644 --- a/src/mainboard/google/veyron_speedy/chromeos.c +++ b/src/mainboard/google/veyron_speedy/chromeos.c @@ -146,4 +146,3 @@ int get_write_protect_state(void) { return !gpio_get(GPIO_WP); } - diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index c5d01ce407..540dfaaf2f 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -468,4 +468,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c index b051518ed6..c85f380bf0 100644 --- a/src/mainboard/hp/dl145_g1/acpi_tables.c +++ b/src/mainboard/hp/dl145_g1/acpi_tables.c @@ -127,4 +127,3 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } - diff --git a/src/mainboard/hp/dl145_g1/devicetree.cb b/src/mainboard/hp/dl145_g1/devicetree.cb index c955ac3b0b..2d4adee0f4 100644 --- a/src/mainboard/hp/dl145_g1/devicetree.cb +++ b/src/mainboard/hp/dl145_g1/devicetree.cb @@ -139,4 +139,3 @@ chip northbridge/amd/amdk8/root_complex end end end - diff --git a/src/mainboard/hp/dl145_g3/devicetree.cb b/src/mainboard/hp/dl145_g3/devicetree.cb index 7012cf97c5..b7f450ec06 100644 --- a/src/mainboard/hp/dl145_g3/devicetree.cb +++ b/src/mainboard/hp/dl145_g3/devicetree.cb @@ -83,5 +83,3 @@ chip northbridge/amd/amdk8/root_complex end #domain end - - diff --git a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb index 2dbcb9b87b..e3213936d1 100644 --- a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb +++ b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb @@ -86,5 +86,3 @@ chip northbridge/amd/amdfam10/root_complex end #domain end - - diff --git a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb index 7de0c8399c..04d6d8d689 100644 --- a/src/mainboard/hp/e_vectra_p2706t/devicetree.cb +++ b/src/mainboard/hp/e_vectra_p2706t/devicetree.cb @@ -56,4 +56,3 @@ chip northbridge/intel/i82810 # Northbridge end end end - diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 02b7f75d2c..a6d66f59b7 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -429,4 +429,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; - diff --git a/src/mainboard/ibm/e325/devicetree.cb b/src/mainboard/ibm/e325/devicetree.cb index bdaee50efa..f63249d02a 100644 --- a/src/mainboard/ibm/e325/devicetree.cb +++ b/src/mainboard/ibm/e325/devicetree.cb @@ -67,4 +67,3 @@ chip northbridge/amd/amdk8/root_complex end end end - diff --git a/src/mainboard/ibm/e326/devicetree.cb b/src/mainboard/ibm/e326/devicetree.cb index 1888987272..32d04a7fa9 100644 --- a/src/mainboard/ibm/e326/devicetree.cb +++ b/src/mainboard/ibm/e326/devicetree.cb @@ -71,4 +71,3 @@ chip northbridge/amd/amdk8/root_complex end end end - diff --git a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb index d5c70330ad..1dffb4bdfe 100644 --- a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb +++ b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb @@ -68,4 +68,3 @@ chip northbridge/amd/amdfam10/root_complex end end #domain end #root_complex - diff --git a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb index a6dba308db..99851b8fd7 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb +++ b/src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb @@ -73,4 +73,3 @@ chip northbridge/amd/lx end end end - diff --git a/src/mainboard/intel/eagleheights/devicetree.cb b/src/mainboard/intel/eagleheights/devicetree.cb index b37750c7e6..8d1549af19 100644 --- a/src/mainboard/intel/eagleheights/devicetree.cb +++ b/src/mainboard/intel/eagleheights/devicetree.cb @@ -70,4 +70,3 @@ chip northbridge/intel/i3100 end end end - diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 1d7bcb0e88..ce42951cf9 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -84,4 +84,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) // Stumpy has no arms^H^H^H^HEC. gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } - diff --git a/src/mainboard/intel/mohonpeak/acpi/platform.asl b/src/mainboard/intel/mohonpeak/acpi/platform.asl index 91f09c76bf..efefb99402 100644 --- a/src/mainboard/intel/mohonpeak/acpi/platform.asl +++ b/src/mainboard/intel/mohonpeak/acpi/platform.asl @@ -62,4 +62,3 @@ Method(_WAK,1) { Return(Package(){0,0}) } - diff --git a/src/mainboard/intel/mohonpeak/cmos.layout b/src/mainboard/intel/mohonpeak/cmos.layout index 6126d2faf2..4353e7d736 100644 --- a/src/mainboard/intel/mohonpeak/cmos.layout +++ b/src/mainboard/intel/mohonpeak/cmos.layout @@ -115,5 +115,3 @@ enumerations checksums checksum 392 415 984 - - diff --git a/src/mainboard/intel/mohonpeak/irq_tables.c b/src/mainboard/intel/mohonpeak/irq_tables.c index 9a066aad43..e7989f7cae 100644 --- a/src/mainboard/intel/mohonpeak/irq_tables.c +++ b/src/mainboard/intel/mohonpeak/irq_tables.c @@ -65,4 +65,3 @@ unsigned long write_pirq_routing_table(unsigned long addr) { return copy_pirq_routing_table(addr, &intel_irq_routing_table); } - diff --git a/src/mainboard/intel/mohonpeak/mainboard.c b/src/mainboard/intel/mohonpeak/mainboard.c index d150286d50..c2a105b375 100644 --- a/src/mainboard/intel/mohonpeak/mainboard.c +++ b/src/mainboard/intel/mohonpeak/mainboard.c @@ -32,4 +32,3 @@ static void mainboard_enable(device_t dev) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; - diff --git a/src/mainboard/iwave/iWRainbowG6/devicetree.cb b/src/mainboard/iwave/iWRainbowG6/devicetree.cb index 29e9e5e38b..9addc14f3d 100644 --- a/src/mainboard/iwave/iWRainbowG6/devicetree.cb +++ b/src/mainboard/iwave/iWRainbowG6/devicetree.cb @@ -39,4 +39,3 @@ chip northbridge/intel/sch end end end - diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb index 50d214be4d..c49c97a048 100644 --- a/src/mainboard/iwill/dk8_htx/devicetree.cb +++ b/src/mainboard/iwill/dk8_htx/devicetree.cb @@ -115,5 +115,3 @@ chip northbridge/amd/amdk8/root_complex end #domain end - - diff --git a/src/mainboard/iwill/dk8s2/devicetree.cb b/src/mainboard/iwill/dk8s2/devicetree.cb index fda8ca2838..21eadb3e5c 100644 --- a/src/mainboard/iwill/dk8s2/devicetree.cb +++ b/src/mainboard/iwill/dk8s2/devicetree.cb @@ -73,4 +73,3 @@ chip northbridge/amd/amdk8/root_complex end end end - diff --git a/src/mainboard/iwill/dk8x/devicetree.cb b/src/mainboard/iwill/dk8x/devicetree.cb index ea7430bccd..d92cd6d5fd 100644 --- a/src/mainboard/iwill/dk8x/devicetree.cb +++ b/src/mainboard/iwill/dk8x/devicetree.cb @@ -54,4 +54,3 @@ chip northbridge/amd/amdk8/root_complex end end end - diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 6043390c23..e08da559b9 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -333,5 +333,3 @@ const PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END }; - - diff --git a/src/mainboard/kontron/kt690/devicetree.cb b/src/mainboard/kontron/kt690/devicetree.cb index 22bdae9b29..3ab33378a3 100644 --- a/src/mainboard/kontron/kt690/devicetree.cb +++ b/src/mainboard/kontron/kt690/devicetree.cb @@ -123,4 +123,3 @@ chip northbridge/amd/amdk8/root_complex end #northbridge/amd/amdk8 end #domain end #northbridge/amd/amdk8/root_complex - diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c index 54ff5d471e..c2fa4bb634 100644 --- a/src/mainboard/kontron/ktqm77/acpi_tables.c +++ b/src/mainboard/kontron/ktqm77/acpi_tables.c @@ -54,4 +54,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } - diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index ac1e40edd4..abbd493327 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -429,4 +429,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; - diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index bb0f1a444f..e8996537ee 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -57,4 +57,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } - diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c index bb0f1a444f..e8996537ee 100644 --- a/src/mainboard/lenovo/t530/acpi_tables.c +++ b/src/mainboard/lenovo/t530/acpi_tables.c @@ -57,4 +57,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } - diff --git a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl index 76b49fa04c..93b45253bd 100644 --- a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl +++ b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl @@ -82,4 +82,3 @@ Method(_PRT) }) } } - diff --git a/src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl index 64712621fa..3ef5d3b44a 100644 --- a/src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl +++ b/src/mainboard/lenovo/x200/acpi/ich9_pci_irqs.asl @@ -106,4 +106,3 @@ If (PICM) { // Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, }) } - diff --git a/src/mainboard/lenovo/x200/acpi/platform.asl b/src/mainboard/lenovo/x200/acpi/platform.asl index edcf641dea..d5cb076f5b 100644 --- a/src/mainboard/lenovo/x200/acpi/platform.asl +++ b/src/mainboard/lenovo/x200/acpi/platform.asl @@ -203,4 +203,3 @@ Scope(\_SB) // TRAP(43) // TODO } } - diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 95659159e4..3fe028e3ec 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -141,4 +141,3 @@ enumerations checksums checksum 392 983 984 - diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 4fb2baf206..d91e225122 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -47,4 +47,3 @@ static void mainboard_enable(device_t dev) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; - diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index a739d18ebf..455dd356d3 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -201,4 +201,3 @@ void main(unsigned long bist) #endif printk(BIOS_SPEW, "exit main()\n"); } - diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c index 75020ff899..9b28f0003e 100644 --- a/src/mainboard/lenovo/x220/acpi_tables.c +++ b/src/mainboard/lenovo/x220/acpi_tables.c @@ -58,4 +58,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } - diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c index 75020ff899..9b28f0003e 100644 --- a/src/mainboard/lenovo/x230/acpi_tables.c +++ b/src/mainboard/lenovo/x230/acpi_tables.c @@ -58,4 +58,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) acpi_update_thermal_table(gnvs); } - diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 23f48b6626..6adabec09b 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -394,4 +394,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb index 239f1f902d..8e6cba0d76 100644 --- a/src/mainboard/lippert/frontrunner/devicetree.cb +++ b/src/mainboard/lippert/frontrunner/devicetree.cb @@ -18,4 +18,3 @@ chip northbridge/amd/gx2 end end end - diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 23f48b6626..6adabec09b 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -394,4 +394,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/msi/ms6178/devicetree.cb b/src/mainboard/msi/ms6178/devicetree.cb index f33e4794d9..ab90fe23ca 100644 --- a/src/mainboard/msi/ms6178/devicetree.cb +++ b/src/mainboard/msi/ms6178/devicetree.cb @@ -81,4 +81,3 @@ chip northbridge/intel/i82810 # Northbridge end end end - diff --git a/src/mainboard/msi/ms9185/devicetree.cb b/src/mainboard/msi/ms9185/devicetree.cb index 013bba3291..3c9168d2ee 100644 --- a/src/mainboard/msi/ms9185/devicetree.cb +++ b/src/mainboard/msi/ms9185/devicetree.cb @@ -83,5 +83,3 @@ chip northbridge/amd/amdk8/root_complex end # amdk8 end #domain end - - diff --git a/src/mainboard/nec/powermate2000/devicetree.cb b/src/mainboard/nec/powermate2000/devicetree.cb index cd4aefe4e5..a3f164e968 100644 --- a/src/mainboard/nec/powermate2000/devicetree.cb +++ b/src/mainboard/nec/powermate2000/devicetree.cb @@ -51,4 +51,3 @@ chip northbridge/intel/i82810 # Northbridge end end end - diff --git a/src/mainboard/newisys/khepri/devicetree.cb b/src/mainboard/newisys/khepri/devicetree.cb index bd00d2884c..8f7455ce27 100644 --- a/src/mainboard/newisys/khepri/devicetree.cb +++ b/src/mainboard/newisys/khepri/devicetree.cb @@ -79,4 +79,3 @@ chip northbridge/amd/amdk8/root_complex end end end - diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c index 73b9fff1b7..2dd9da8b9c 100644 --- a/src/mainboard/packardbell/ms2290/acpi_tables.c +++ b/src/mainboard/packardbell/ms2290/acpi_tables.c @@ -34,4 +34,3 @@ void acpi_create_gnvs(global_nvs_t * gnvs) { } - diff --git a/src/mainboard/pcengines/alix1c/devicetree.cb b/src/mainboard/pcengines/alix1c/devicetree.cb index 85e967ad86..20e865ab60 100644 --- a/src/mainboard/pcengines/alix1c/devicetree.cb +++ b/src/mainboard/pcengines/alix1c/devicetree.cb @@ -83,4 +83,3 @@ chip northbridge/amd/lx end end - diff --git a/src/mainboard/pcengines/alix2d/devicetree.cb b/src/mainboard/pcengines/alix2d/devicetree.cb index d8aa3bc491..f8368ed7fa 100644 --- a/src/mainboard/pcengines/alix2d/devicetree.cb +++ b/src/mainboard/pcengines/alix2d/devicetree.cb @@ -43,4 +43,3 @@ chip northbridge/amd/lx end end - diff --git a/src/mainboard/pcengines/alix6/board_info.txt b/src/mainboard/pcengines/alix6/board_info.txt index db8bbb2de3..6af0ddf53f 100644 --- a/src/mainboard/pcengines/alix6/board_info.txt +++ b/src/mainboard/pcengines/alix6/board_info.txt @@ -2,4 +2,3 @@ Category: half Board URL: http://pcengines.ch/alix6f2.htm Flashrom support: y Clone of: pcengines/alix2d - diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index f3db4f0202..03c5d1725b 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -403,4 +403,3 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { */ #include "mm.h" #include "mn.h" - diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb index d39126ce79..7c31423c6d 100644 --- a/src/mainboard/rca/rm4100/devicetree.cb +++ b/src/mainboard/rca/rm4100/devicetree.cb @@ -65,4 +65,3 @@ chip northbridge/intel/i82830 # Northbridge end end end - diff --git a/src/mainboard/roda/rk9/Makefile.inc b/src/mainboard/roda/rk9/Makefile.inc index d6838b7b4b..aa59e72524 100644 --- a/src/mainboard/roda/rk9/Makefile.inc +++ b/src/mainboard/roda/rk9/Makefile.inc @@ -19,4 +19,3 @@ ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += ti_pci7xx1.c ramstage-y += cstates.c - diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index 04e3bd0fb6..f6275b4df8 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -85,4 +85,3 @@ void acpi_create_gnvs(global_nvs_t *gnvs) // Stumpy has no arms^H^H^H^HEC. gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; } - diff --git a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c index dbb3229896..3337c6d9d1 100644 --- a/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/acpi_tables.c @@ -105,4 +105,3 @@ void mainboard_inject_dsdt(device_t device) acpigen_pop_len(); } } - diff --git a/src/mainboard/siemens/sitemp_g1p1/devicetree.cb b/src/mainboard/siemens/sitemp_g1p1/devicetree.cb index 1d83f10579..e47703f738 100644 --- a/src/mainboard/siemens/sitemp_g1p1/devicetree.cb +++ b/src/mainboard/siemens/sitemp_g1p1/devicetree.cb @@ -132,4 +132,3 @@ chip northbridge/amd/amdk8/root_complex end #northbridge/amd/amdk8 end #domain end #northbridge/amd/amdk8/root_complex - diff --git a/src/mainboard/supermicro/h8dmr_fam10/README b/src/mainboard/supermicro/h8dmr_fam10/README index 485e7c852c..1d7bbdc822 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/README +++ b/src/mainboard/supermicro/h8dmr_fam10/README @@ -20,4 +20,3 @@ disabled in CBFS. I'm not sure what's causing this particular slowness. See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/052107.html Ward, 2009-09-22 - diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index 2ee1353252..f5d69d4ab7 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -74,4 +74,3 @@ config VGA_BIOS_ID default "102b,0532" endif # BOARD_SUPERMICRO_H8QGI - diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb index 2622209be0..59740c9b5b 100644 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -135,4 +135,3 @@ chip northbridge/amd/agesa/family15/root_complex end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family15/root_complex - diff --git a/src/mainboard/supermicro/h8scm/devicetree.cb b/src/mainboard/supermicro/h8scm/devicetree.cb index 2529902ce1..b8fb82335b 100644 --- a/src/mainboard/supermicro/h8scm/devicetree.cb +++ b/src/mainboard/supermicro/h8scm/devicetree.cb @@ -130,4 +130,3 @@ chip northbridge/amd/agesa/family15/root_complex end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family15/root_complex - diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb index 9dda5d8150..82229da9ba 100644 --- a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb @@ -121,5 +121,3 @@ chip northbridge/amd/amdfam10/root_complex # end #domain end - - diff --git a/src/mainboard/technexion/tim5690/devicetree.cb b/src/mainboard/technexion/tim5690/devicetree.cb index 23b9741b9f..bf462e213a 100644 --- a/src/mainboard/technexion/tim5690/devicetree.cb +++ b/src/mainboard/technexion/tim5690/devicetree.cb @@ -110,4 +110,3 @@ chip northbridge/amd/amdk8/root_complex end #northbridge/amd/amdk8 end #domain end #northbridge/amd/amdk8/root_complex - diff --git a/src/mainboard/technexion/tim8690/devicetree.cb b/src/mainboard/technexion/tim8690/devicetree.cb index ff14075563..8d1df8be10 100644 --- a/src/mainboard/technexion/tim8690/devicetree.cb +++ b/src/mainboard/technexion/tim8690/devicetree.cb @@ -113,4 +113,3 @@ chip northbridge/amd/amdk8/root_complex end #northbridge/amd/amdk8 end #domain end #northbridge/amd/amdk8/root_complex - diff --git a/src/mainboard/tyan/s2735/devicetree.cb b/src/mainboard/tyan/s2735/devicetree.cb index d3b6b1eefe..866bdc510e 100644 --- a/src/mainboard/tyan/s2735/devicetree.cb +++ b/src/mainboard/tyan/s2735/devicetree.cb @@ -83,4 +83,3 @@ chip northbridge/intel/e7501 end end end - diff --git a/src/mainboard/tyan/s2850/devicetree.cb b/src/mainboard/tyan/s2850/devicetree.cb index 85c63848df..2698542401 100644 --- a/src/mainboard/tyan/s2850/devicetree.cb +++ b/src/mainboard/tyan/s2850/devicetree.cb @@ -93,4 +93,3 @@ chip northbridge/amd/amdk8/root_complex end end end - diff --git a/src/mainboard/tyan/s2875/devicetree.cb b/src/mainboard/tyan/s2875/devicetree.cb index 39eb8b2364..bdb4705ed5 100644 --- a/src/mainboard/tyan/s2875/devicetree.cb +++ b/src/mainboard/tyan/s2875/devicetree.cb @@ -85,4 +85,3 @@ chip northbridge/amd/amdk8/root_complex end end end - diff --git a/src/mainboard/tyan/s2880/devicetree.cb b/src/mainboard/tyan/s2880/devicetree.cb index f9f48566ea..3e18f5529f 100644 --- a/src/mainboard/tyan/s2880/devicetree.cb +++ b/src/mainboard/tyan/s2880/devicetree.cb @@ -96,4 +96,3 @@ chip northbridge/amd/amdk8/root_complex end end end - diff --git a/src/mainboard/tyan/s2881/devicetree.cb b/src/mainboard/tyan/s2881/devicetree.cb index aab75a3939..7d0ed5e604 100644 --- a/src/mainboard/tyan/s2881/devicetree.cb +++ b/src/mainboard/tyan/s2881/devicetree.cb @@ -127,4 +127,3 @@ chip northbridge/amd/amdk8/root_complex end end end - diff --git a/src/mainboard/tyan/s2882/devicetree.cb b/src/mainboard/tyan/s2882/devicetree.cb index 40746956b3..74a26d0233 100644 --- a/src/mainboard/tyan/s2882/devicetree.cb +++ b/src/mainboard/tyan/s2882/devicetree.cb @@ -123,4 +123,3 @@ chip northbridge/amd/amdk8/root_complex end # NB end #domain end - diff --git a/src/mainboard/tyan/s2885/devicetree.cb b/src/mainboard/tyan/s2885/devicetree.cb index 7191e5216f..97a18e5a69 100644 --- a/src/mainboard/tyan/s2885/devicetree.cb +++ b/src/mainboard/tyan/s2885/devicetree.cb @@ -120,4 +120,3 @@ chip northbridge/amd/amdk8/root_complex end #domain end - diff --git a/src/mainboard/tyan/s4880/devicetree.cb b/src/mainboard/tyan/s4880/devicetree.cb index da59eb5b9c..d64d054c29 100644 --- a/src/mainboard/tyan/s4880/devicetree.cb +++ b/src/mainboard/tyan/s4880/devicetree.cb @@ -96,4 +96,3 @@ chip northbridge/amd/amdk8/root_complex end #domain end - diff --git a/src/mainboard/tyan/s4882/devicetree.cb b/src/mainboard/tyan/s4882/devicetree.cb index 44da2c29a2..0eb59afdd1 100644 --- a/src/mainboard/tyan/s4882/devicetree.cb +++ b/src/mainboard/tyan/s4882/devicetree.cb @@ -193,4 +193,3 @@ chip northbridge/amd/amdk8/root_complex end end - diff --git a/src/mainboard/tyan/s8226/devicetree.cb b/src/mainboard/tyan/s8226/devicetree.cb index 0080d6295f..64701a5e99 100644 --- a/src/mainboard/tyan/s8226/devicetree.cb +++ b/src/mainboard/tyan/s8226/devicetree.cb @@ -130,4 +130,3 @@ chip northbridge/amd/agesa/family15/root_complex end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family15/root_complex - diff --git a/src/mainboard/via/vt8454c/Kconfig b/src/mainboard/via/vt8454c/Kconfig index da71c8796b..408206c7f0 100644 --- a/src/mainboard/via/vt8454c/Kconfig +++ b/src/mainboard/via/vt8454c/Kconfig @@ -24,4 +24,3 @@ config IRQ_SLOT_COUNT default 15 endif # BOARD_VIA_VT8454C - diff --git a/src/mainboard/via/vt8454c/devicetree.cb b/src/mainboard/via/vt8454c/devicetree.cb index 87d2ed1502..efb5b6c67a 100644 --- a/src/mainboard/via/vt8454c/devicetree.cb +++ b/src/mainboard/via/vt8454c/devicetree.cb @@ -51,4 +51,3 @@ chip northbridge/via/cx700 #device pci 12.0 on end # Ethernet end # pci domain 0 end # cx700 - diff --git a/src/mainboard/winent/pl6064/devicetree.cb b/src/mainboard/winent/pl6064/devicetree.cb index f900f78b5a..20d7561e6e 100644 --- a/src/mainboard/winent/pl6064/devicetree.cb +++ b/src/mainboard/winent/pl6064/devicetree.cb @@ -78,4 +78,3 @@ chip northbridge/amd/lx end end end - diff --git a/src/mainboard/wyse/s50/devicetree.cb b/src/mainboard/wyse/s50/devicetree.cb index d433ba3204..5f0435d917 100644 --- a/src/mainboard/wyse/s50/devicetree.cb +++ b/src/mainboard/wyse/s50/devicetree.cb @@ -48,4 +48,3 @@ chip northbridge/amd/gx2 end end end - diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h index fcec368409..785f67799a 100644 --- a/src/northbridge/amd/amdfam10/ht_config.h +++ b/src/northbridge/amd/amdfam10/ht_config.h @@ -51,5 +51,3 @@ void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 io_min, u32 io_max); void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes); - - diff --git a/src/northbridge/intel/e7501/Kconfig b/src/northbridge/intel/e7501/Kconfig index 496894f952..91af6c464b 100644 --- a/src/northbridge/intel/e7501/Kconfig +++ b/src/northbridge/intel/e7501/Kconfig @@ -2,4 +2,3 @@ config NORTHBRIDGE_INTEL_E7501 bool select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT - diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c index 9e01d774fa..1e20945138 100644 --- a/src/northbridge/intel/fsp_sandybridge/acpi.c +++ b/src/northbridge/intel/fsp_sandybridge/acpi.c @@ -210,4 +210,3 @@ void *igd_make_opregion(void) init_igd_opregion(opregion); return opregion; } - diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 9ac8d734fc..04e234ca03 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -34,4 +34,3 @@ config SDRAMPWR_4DIMM If your board has 4 DIMM slots, you must use select this option, in your Kconfig file of the board. On boards with 3 DIMM slots, do _not_ select this option. - diff --git a/src/northbridge/intel/i440lx/Kconfig b/src/northbridge/intel/i440lx/Kconfig index 10c39775ee..b087774b45 100644 --- a/src/northbridge/intel/i440lx/Kconfig +++ b/src/northbridge/intel/i440lx/Kconfig @@ -21,4 +21,3 @@ config NORTHBRIDGE_INTEL_I440LX bool select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT - diff --git a/src/northbridge/intel/i82810/Kconfig b/src/northbridge/intel/i82810/Kconfig index 3ed746fafe..dc4c087574 100644 --- a/src/northbridge/intel/i82810/Kconfig +++ b/src/northbridge/intel/i82810/Kconfig @@ -47,4 +47,3 @@ config VGA_BIOS_ID string default "8086,7121" depends on NORTHBRIDGE_INTEL_I82810 - diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig index 662840fcce..25a9e97587 100644 --- a/src/northbridge/intel/i82830/Kconfig +++ b/src/northbridge/intel/i82830/Kconfig @@ -26,4 +26,3 @@ config VIDEO_MB default 1 if I830_VIDEO_MB_1MB default 8 if I830_VIDEO_MB_8MB depends on NORTHBRIDGE_INTEL_I82830 - diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index 1fe7f490c7..57ca3666ef 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -211,4 +211,3 @@ void *igd_make_opregion(void) init_igd_opregion(opregion); return opregion; } - diff --git a/src/northbridge/via/cn700/Kconfig b/src/northbridge/via/cn700/Kconfig index 15c86ebc77..18897054d8 100644 --- a/src/northbridge/via/cn700/Kconfig +++ b/src/northbridge/via/cn700/Kconfig @@ -35,4 +35,3 @@ config VIDEO_MB default 64 if CN700_VIDEO_MB_64MB default 128 if CN700_VIDEO_MB_128MB depends on NORTHBRIDGE_VIA_CN700 - diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig index a59fc419ae..9eb84fb14e 100644 --- a/src/northbridge/via/vx800/Kconfig +++ b/src/northbridge/via/vx800/Kconfig @@ -3,4 +3,3 @@ config NORTHBRIDGE_VIA_VX800 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select LATE_CBMEM_INIT - diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index 9aac58f7e9..a8369ec210 100755 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -1659,5 +1659,3 @@ done: // free_heap(); return; } - - diff --git a/src/soc/broadcom/cygnus/ddr_init_table.c b/src/soc/broadcom/cygnus/ddr_init_table.c index 5faa1de197..d9258958c7 100644 --- a/src/soc/broadcom/cygnus/ddr_init_table.c +++ b/src/soc/broadcom/cygnus/ddr_init_table.c @@ -1808,4 +1808,3 @@ const unsigned int ddr2_mode_reg_tab[] = { 0x0000 }; #endif - diff --git a/src/soc/broadcom/cygnus/include/soc/cygnus.h b/src/soc/broadcom/cygnus/include/soc/cygnus.h index a314c739ac..d447c754ee 100644 --- a/src/soc/broadcom/cygnus/include/soc/cygnus.h +++ b/src/soc/broadcom/cygnus/include/soc/cygnus.h @@ -23,4 +23,3 @@ void usb_init(void); #endif - diff --git a/src/soc/broadcom/cygnus/include/soc/cygnus_types.h b/src/soc/broadcom/cygnus/include/soc/cygnus_types.h index f65a0d19e4..7466024c03 100644 --- a/src/soc/broadcom/cygnus/include/soc/cygnus_types.h +++ b/src/soc/broadcom/cygnus/include/soc/cygnus_types.h @@ -41,4 +41,3 @@ typedef int32_t int32; typedef uint32_t uint32; #endif - diff --git a/src/soc/broadcom/cygnus/include/soc/ddr_bist.h b/src/soc/broadcom/cygnus/include/soc/ddr_bist.h index 09868ca4c2..007a80aa48 100755 --- a/src/soc/broadcom/cygnus/include/soc/ddr_bist.h +++ b/src/soc/broadcom/cygnus/include/soc/ddr_bist.h @@ -157,4 +157,3 @@ enum drc_reg_set { #endif /* #ifndef __SOC_BROADCOM_CYGNUS_DDR_BIST_H__*/ /* End of File */ - diff --git a/src/soc/broadcom/cygnus/include/soc/reg_utils.h b/src/soc/broadcom/cygnus/include/soc/reg_utils.h index fb2e4dea3e..e276613537 100755 --- a/src/soc/broadcom/cygnus/include/soc/reg_utils.h +++ b/src/soc/broadcom/cygnus/include/soc/reg_utils.h @@ -179,4 +179,3 @@ reg8_read(volatile uint8_t *reg) return *reg; } #endif /* __SOC_BROADCOM_CYGNUS_REG_UTILS__ */ - diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h index c73d512479..0efd3ac5e9 100755 --- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h +++ b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h @@ -1148,4 +1148,3 @@ extern int soc_ydc_ddr_bist_run(int unit, int phy_ndx, #endif /* #ifndef __SOC_BROADCOM_CYGNUS_YDC_DDR_BIST_H__ */ /* End of File */ - diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 9d46c12da2..7c6a67faff 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -282,4 +282,3 @@ fixed_mtrr_table: .word 0x26B, 0x26C, 0x26D .word 0x26E, 0x26F fixed_mtrr_table_end: - diff --git a/src/soc/intel/braswell/romstage/cache_as_ram.inc b/src/soc/intel/braswell/romstage/cache_as_ram.inc index 9d46c12da2..7c6a67faff 100644 --- a/src/soc/intel/braswell/romstage/cache_as_ram.inc +++ b/src/soc/intel/braswell/romstage/cache_as_ram.inc @@ -282,4 +282,3 @@ fixed_mtrr_table: .word 0x26B, 0x26C, 0x26D .word 0x26E, 0x26F fixed_mtrr_table_end: - diff --git a/src/soc/intel/broadwell/acpi/irqlinks.asl b/src/soc/intel/broadwell/acpi/irqlinks.asl index f84b5140cc..92b1801ce1 100644 --- a/src/soc/intel/broadwell/acpi/irqlinks.asl +++ b/src/soc/intel/broadwell/acpi/irqlinks.asl @@ -489,4 +489,3 @@ Device (LNKH) } } } - diff --git a/src/soc/intel/broadwell/acpi/pci_irqs.asl b/src/soc/intel/broadwell/acpi/pci_irqs.asl index f361f8edaa..ed28bab93b 100644 --- a/src/soc/intel/broadwell/acpi/pci_irqs.asl +++ b/src/soc/intel/broadwell/acpi/pci_irqs.asl @@ -86,4 +86,3 @@ Method(_PRT) }) } } - diff --git a/src/soc/intel/broadwell/acpi/smbus.asl b/src/soc/intel/broadwell/acpi/smbus.asl index e19aeff897..b16d1293c1 100644 --- a/src/soc/intel/broadwell/acpi/smbus.asl +++ b/src/soc/intel/broadwell/acpi/smbus.asl @@ -238,4 +238,3 @@ Device (SBUS) } #endif } - diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl index e407b84b99..b373ce716e 100644 --- a/src/soc/intel/broadwell/acpi/xhci.asl +++ b/src/soc/intel/broadwell/acpi/xhci.asl @@ -368,4 +368,3 @@ Device (XHCI) Device (PRT6) { Name (_ADR, 6) } // USB Port 5 } } - diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 6eb5bb31a8..ae8dc73684 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -164,4 +164,3 @@ static const struct pci_driver pch_adsp __pci_driver = { .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; - diff --git a/src/soc/intel/broadwell/bootblock/timestamp.inc b/src/soc/intel/broadwell/bootblock/timestamp.inc index f565775ed8..3db5c35c4d 100644 --- a/src/soc/intel/broadwell/bootblock/timestamp.inc +++ b/src/soc/intel/broadwell/bootblock/timestamp.inc @@ -16,4 +16,3 @@ stash_timestamp: /* Restore the BIST value to %eax */ movl %ebp, %eax - diff --git a/src/soc/intel/broadwell/microcode/microcode_blob.c b/src/soc/intel/broadwell/microcode/microcode_blob.c index 1df4a4fc89..412fedcba1 100644 --- a/src/soc/intel/broadwell/microcode/microcode_blob.c +++ b/src/soc/intel/broadwell/microcode/microcode_blob.c @@ -20,4 +20,3 @@ unsigned microcode[] = { #include "../../../../../3rdparty/blobs/soc/intel/broadwell/microcode_blob.h" }; - diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index 4f1fdb8cfc..ba90c25c72 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -338,4 +338,3 @@ mtrr_table: .word 0x20C, 0x20D, 0x20E, 0x20F .word 0x210, 0x211, 0x212, 0x213 mtrr_table_end: - diff --git a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl b/src/soc/intel/fsp_baytrail/acpi/irqroute.asl index 535913729e..aa9b5de96d 100644 --- a/src/soc/intel/fsp_baytrail/acpi/irqroute.asl +++ b/src/soc/intel/fsp_baytrail/acpi/irqroute.asl @@ -47,4 +47,3 @@ PCIE_BRIDGE_IRQ_ROUTES #undef PIC_MODE #include "irq_helper.h" PCIE_BRIDGE_IRQ_ROUTES - diff --git a/src/soc/marvell/bg4cd/include/soc/i2c.h b/src/soc/marvell/bg4cd/include/soc/i2c.h index 2cd7ee6998..fcae571900 100644 --- a/src/soc/marvell/bg4cd/include/soc/i2c.h +++ b/src/soc/marvell/bg4cd/include/soc/i2c.h @@ -23,4 +23,3 @@ void i2c_init(unsigned int bus, unsigned int hz); #endif - diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c index 1c0774f06e..5520c4f325 100644 --- a/src/soc/nvidia/tegra/usb.c +++ b/src/soc/nvidia/tegra/usb.c @@ -216,4 +216,3 @@ void usb_setup_utmip(void *usb_base) usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP); printk(BIOS_DEBUG, "USB controller @ %p set up with UTMI+ PHY\n",usb_base); } - diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 29513d4517..e07debc022 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -342,4 +342,3 @@ void display_startup(device_t dev) edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel; set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); } - diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 3133d0f76a..3c92ef4993 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -307,4 +307,3 @@ void sor_clock_stop(void); void sor_clock_start(void); #endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */ - diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h index 8844827ef9..fc78943030 100644 --- a/src/soc/nvidia/tegra132/include/soc/clock.h +++ b/src/soc/nvidia/tegra132/include/soc/clock.h @@ -410,4 +410,3 @@ void sor_clock_start(void); void clock_enable_audio(void); #endif /* __SOC_NVIDIA_TEGRA132_CLOCK_H__ */ - diff --git a/src/soc/qualcomm/ipq806x/gpio.c b/src/soc/qualcomm/ipq806x/gpio.c index c40b521101..35a3283bce 100644 --- a/src/soc/qualcomm/ipq806x/gpio.c +++ b/src/soc/qualcomm/ipq806x/gpio.c @@ -151,4 +151,3 @@ void gpio_input(gpio_t gpio) gpio_tlmm_config_set(gpio, GPIO_FUNC_DISABLE, GPIO_NO_PULL, GPIO_2MA, GPIO_DISABLE); } - diff --git a/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h b/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h index 4e1ef34294..7bbce24df0 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h +++ b/src/soc/qualcomm/ipq806x/include/soc/ipq_timer.h @@ -36,5 +36,3 @@ #define DGT_ENABLE_EN 1 #define SPSS_TIMER_STATUS_DGT_EN (1 << 0) - - diff --git a/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h b/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h index f1b05b0c0c..f499b9b390 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h +++ b/src/soc/qualcomm/ipq806x/include/soc/ipq_uart.h @@ -270,4 +270,3 @@ enum MSM_BOOT_UART_DM_BITS_PER_CHAR { void ipq806x_uart_init(void); #endif /* __UART_DM_H__ */ - diff --git a/src/soc/qualcomm/ipq806x/mbn_header.h b/src/soc/qualcomm/ipq806x/mbn_header.h index 96e6ae7a4b..a58242b9a2 100644 --- a/src/soc/qualcomm/ipq806x/mbn_header.h +++ b/src/soc/qualcomm/ipq806x/mbn_header.h @@ -34,4 +34,3 @@ struct mbn_header { }; #endif - diff --git a/src/soc/rockchip/rk3288/include/soc/i2c.h b/src/soc/rockchip/rk3288/include/soc/i2c.h index 9162df0599..2e0d5c5acc 100644 --- a/src/soc/rockchip/rk3288/include/soc/i2c.h +++ b/src/soc/rockchip/rk3288/include/soc/i2c.h @@ -25,4 +25,3 @@ void software_i2c_attach(unsigned bus); void software_i2c_detach(unsigned bus); #endif - diff --git a/src/soc/rockchip/rk3288/include/soc/pwm.h b/src/soc/rockchip/rk3288/include/soc/pwm.h index 3b70858494..0240556c29 100644 --- a/src/soc/rockchip/rk3288/include/soc/pwm.h +++ b/src/soc/rockchip/rk3288/include/soc/pwm.h @@ -23,4 +23,3 @@ void pwm_init(u32 id, u32 period_ns, u32 duty_ns); #endif - diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index eeb35c7626..db6aa929a8 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -303,4 +303,3 @@ void exynos5420_config_smp(void) init_exynos_cpu_states(); configure_secondary_cores(); } - diff --git a/src/southbridge/amd/amd8131/Kconfig b/src/southbridge/amd/amd8131/Kconfig index 30f3f46818..f3418dc93c 100644 --- a/src/southbridge/amd/amd8131/Kconfig +++ b/src/southbridge/amd/amd8131/Kconfig @@ -19,4 +19,3 @@ config SOUTHBRIDGE_AMD_AMD8131 bool - diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig index 728ee45f95..e0bffab7f0 100644 --- a/src/southbridge/amd/cimx/sb700/Kconfig +++ b/src/southbridge/amd/cimx/sb700/Kconfig @@ -68,4 +68,3 @@ config REDIRECT_SBCIMX_TRACE_TO_SERIAL Warning: Only enable this option when debuging or tracing AMD CIMX code. endif #SOUTHBRIDGE_AMD_CIMX_SB700 - diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 3331f2ff44..4bbdb4a3c4 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -223,4 +223,3 @@ config SB800_IMC_FAN_CONTROL endchoice endif #SOUTHBRIDGE_AMD_CIMX_SB800 - diff --git a/src/southbridge/amd/cimx/sb900/Kconfig b/src/southbridge/amd/cimx/sb900/Kconfig index c9da62a849..4693bb2d3a 100644 --- a/src/southbridge/amd/cimx/sb900/Kconfig +++ b/src/southbridge/amd/cimx/sb900/Kconfig @@ -55,4 +55,3 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT default "southbridge/amd/cimx/sb900/bootblock.c" endif #SOUTHBRIDGE_AMD_CIMX_SB900 - diff --git a/src/southbridge/amd/cs5536/Kconfig b/src/southbridge/amd/cs5536/Kconfig index dc628ecef6..95abc92ca5 100644 --- a/src/southbridge/amd/cs5536/Kconfig +++ b/src/southbridge/amd/cs5536/Kconfig @@ -20,4 +20,3 @@ config SOUTHBRIDGE_AMD_CS5536 bool select UDELAY_TSC - diff --git a/src/southbridge/amd/rs780/Kconfig b/src/southbridge/amd/rs780/Kconfig index ad777b993f..f0a392f1d7 100644 --- a/src/southbridge/amd/rs780/Kconfig +++ b/src/southbridge/amd/rs780/Kconfig @@ -19,4 +19,3 @@ config SOUTHBRIDGE_AMD_RS780 bool - diff --git a/src/southbridge/intel/i3100/Kconfig b/src/southbridge/intel/i3100/Kconfig index eef30ef5d7..1dd0931779 100644 --- a/src/southbridge/intel/i3100/Kconfig +++ b/src/southbridge/intel/i3100/Kconfig @@ -10,4 +10,3 @@ config HPET_MIN_TICKS default 0x90 endif - diff --git a/src/southbridge/intel/i82801ax/Kconfig b/src/southbridge/intel/i82801ax/Kconfig index 41e0b33105..7899faa74e 100644 --- a/src/southbridge/intel/i82801ax/Kconfig +++ b/src/southbridge/intel/i82801ax/Kconfig @@ -22,4 +22,3 @@ config SOUTHBRIDGE_INTEL_I82801AX select IOAPIC select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT - diff --git a/src/southbridge/intel/i82801bx/Kconfig b/src/southbridge/intel/i82801bx/Kconfig index 0378213893..f0e8e9db9f 100644 --- a/src/southbridge/intel/i82801bx/Kconfig +++ b/src/southbridge/intel/i82801bx/Kconfig @@ -22,4 +22,3 @@ config SOUTHBRIDGE_INTEL_I82801BX select IOAPIC select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT - diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index af526c3fdd..acbac83ec1 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -42,4 +42,3 @@ config HPET_MIN_TICKS default 0x80 endif - diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 9b2d4ce026..77fb6344fb 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -43,4 +43,3 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT default "southbridge/intel/i82801ix/bootblock.c" endif - diff --git a/src/southbridge/intel/sch/Kconfig b/src/southbridge/intel/sch/Kconfig index fc90f262bd..23bee0ea00 100644 --- a/src/southbridge/intel/sch/Kconfig +++ b/src/southbridge/intel/sch/Kconfig @@ -51,4 +51,3 @@ config HPET_MIN_TICKS default 0x80 endif - diff --git a/src/southbridge/ricoh/rl5c476/Kconfig b/src/southbridge/ricoh/rl5c476/Kconfig index a2f1386a9d..86e8ab9821 100644 --- a/src/southbridge/ricoh/rl5c476/Kconfig +++ b/src/southbridge/ricoh/rl5c476/Kconfig @@ -19,4 +19,3 @@ config SOUTHBRIDGE_RICOH_RL5C476 bool - diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 1fbd57d7dc..390589ce0c 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -11,4 +11,3 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT config EHCI_BAR hex default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 - diff --git a/src/southbridge/ti/pci7420/Kconfig b/src/southbridge/ti/pci7420/Kconfig index 9bd610d762..1bfe01144c 100644 --- a/src/southbridge/ti/pci7420/Kconfig +++ b/src/southbridge/ti/pci7420/Kconfig @@ -19,4 +19,3 @@ config SOUTHBRIDGE_TI_PCI7420 bool - diff --git a/src/southbridge/ti/pcixx12/Kconfig b/src/southbridge/ti/pcixx12/Kconfig index d306efafbb..d7cfc17427 100644 --- a/src/southbridge/ti/pcixx12/Kconfig +++ b/src/southbridge/ti/pcixx12/Kconfig @@ -19,4 +19,3 @@ config SOUTHBRIDGE_TI_PCIXX12 bool - |