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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2017-10-24 17:41:19 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2017-11-03 07:14:20 +0000 |
| commit | 545593d62c613a4053b8ce154c22668a6d37c733 (patch) | |
| tree | 50d0b7e769cfb8f6a3a97e50532c7b9f4b592ad5 /src | |
| parent | ee2dae2f17952cbd87148a9a33b847cdbe0af4dc (diff) | |
| download | coreboot-545593d62c613a4053b8ce154c22668a6d37c733.tar.xz | |
soc/intel/apollolake: Add APL CPU device ID
Add Apollo Lake CPU device ID for E0 stepping.
Change-Id: I28fa222cd28b783d22c347cdbbd769e66bf10c30
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/apollolake/cpu.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/cpu.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/mp_init.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/mp_init.h | 1 |
4 files changed, 3 insertions, 5 deletions
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 75f6c490e2..d2c7001ede 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -106,6 +106,7 @@ static struct device_operations cpu_dev_ops = { static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 }, + { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, { 0, 0 }, diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 2d22ae5181..ed4a7de477 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -18,11 +18,6 @@ #ifndef _SOC_APOLLOLAKE_CPU_H_ #define _SOC_APOLLOLAKE_CPU_H_ -#define CPUID_APOLLOLAKE_A0 0x506c8 -#define CPUID_APOLLOLAKE_B0 0x506c9 -#define CPUID_GLK_A0 0x706a0 -#define CPUID_GLK_B0 0x706a1 - /* Common Timer Copy (CTC) frequency - 19.2MHz. */ #define CTC_FREQ 19200000 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index c08d251469..e301c24447 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -65,6 +65,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_CANNONLAKE_C0 }, { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 }, { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 }, + { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0 }, { X86_VENDOR_INTEL, CPUID_GLK_A0 }, { X86_VENDOR_INTEL, CPUID_GLK_B0 }, { 0, 0 }, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 640be76a91..ab3e1edfde 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -33,6 +33,7 @@ #define CPUID_CANNONLAKE_C0 0x60662 #define CPUID_APOLLOLAKE_A0 0x506c8 #define CPUID_APOLLOLAKE_B0 0x506c9 +#define CPUID_APOLLOLAKE_E0 0x506ca #define CPUID_GLK_A0 0x706a0 #define CPUID_GLK_B0 0x706a1 |