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authorGreg Watson <jarrah@users.sourceforge.net>2003-07-21 03:38:42 +0000
committerGreg Watson <jarrah@users.sourceforge.net>2003-07-21 03:38:42 +0000
commit54b3d233ed4a66bc9fbc8af7dd742af7d8f2aca3 (patch)
tree03bf5f3700f3da4a12abdf92ef9ba61301b613ad /src
parentd0580343b6c81697f0050b38ea36ee154d242ac2 (diff)
downloadcoreboot-54b3d233ed4a66bc9fbc8af7dd742af7d8f2aca3.tar.xz
more chip stuff
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/superio/NSC/pc97307/chip.h17
-rw-r--r--src/superio/NSC/pc97307/superio.c29
2 files changed, 25 insertions, 21 deletions
diff --git a/src/superio/NSC/pc97307/chip.h b/src/superio/NSC/pc97307/chip.h
index d30b7cb26c..4839ae54f1 100644
--- a/src/superio/NSC/pc97307/chip.h
+++ b/src/superio/NSC/pc97307/chip.h
@@ -1,5 +1,18 @@
+#ifndef PNP_INDEX_REG
+#define PNP_INDEX_REG 0x15C
+#endif
+#ifndef PNP_DATA_REG
+#define PNP_DATA_REG 0x15D
+#endif
+#ifndef SIO_COM1
+#define SIO_COM1_BASE 0x3F8
+#endif
+#ifndef SIO_COM2
+#define SIO_COM2_BASE 0x2F8
+#endif
struct superio_NSC_pc97307_config {
- typedef struct com_ports com1;
- typedef struct lpt_ports lpt;
+ struct com_ports com1;
+ struct lpt_ports lpt;
+ int port;
};
diff --git a/src/superio/NSC/pc97307/superio.c b/src/superio/NSC/pc97307/superio.c
index 00117d8f32..100fa146d9 100644
--- a/src/superio/NSC/pc97307/superio.c
+++ b/src/superio/NSC/pc97307/superio.c
@@ -3,19 +3,7 @@
#include <arch/io.h>
#include <device/chip.h>
-
-#ifndef PNP_INDEX_REG
-#define PNP_INDEX_REG 0x15C
-#endif
-#ifndef PNP_DATA_REG
-#define PNP_DATA_REG 0x15D
-#endif
-#ifndef SIO_COM1
-#define SIO_COM1_BASE 0x3F8
-#endif
-#ifndef SIO_COM2
-#define SIO_COM2_BASE 0x2F8
-#endif
+#include "chip.h"
void pnp_output(char address, char data)
{
@@ -25,22 +13,25 @@ void pnp_output(char address, char data)
void sio_enable(struct chip *chip, enum chip_pass pass)
{
+
+ struct superio_NSC_pc97307_config *conf = (struct superio_NSC_pc97307_config *)chip->chip_info;
+
switch (pass) {
case CHIP_PRE_CONSOLE:
/* Enable Super IO Chip */
pnp_output(0x07, 6); /* LD 6 = UART1 */
pnp_output(0x30, 0); /* Dectivate */
- pnp_output(0x60, chip->control->defaultport >> 8); /* IO Base */
- pnp_output(0x61, chip->control->defaultport & 0xFF); /* IO Base */
+ pnp_output(0x60, conf->port >> 8); /* IO Base */
+ pnp_output(0x61, conf->port & 0xFF); /* IO Base */
pnp_output(0x30, 1); /* Activate */
break;
default:
/* nothing yet */
+ break;
}
}
-struct superio_control superio_NSC_pc97307_control = {
- enable: sio_enable,
- defaultport: SIO_COM1_BASE,
- name: "NSC 87307"
+struct chip_control superio_NSC_pc97307_control = {
+ enable: sio_enable,
+ name: "NSC 87307"
};