diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-03-31 14:34:40 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-03-31 14:34:40 +0000 |
| commit | 5a1f5970857a5ad1fda0cf9d5945192408bf537b (patch) | |
| tree | b81a16a564c29788dcb6c306ea27855703d230de /src | |
| parent | b8ac05d187c6cc4e777c96d39e075c5d97d93ffc (diff) | |
| download | coreboot-5a1f5970857a5ad1fda0cf9d5945192408bf537b.tar.xz | |
This patch drops arch/i386/lib/console.c and arch/i386/lib/console_print.c and
makes include/console/console.h and console/console.c usable both in
__PRE_RAM__ and coreboot_ram stages.
While debugging this, I removed an indirection from the e7520 ram init code
(same as we did on a couple of other chipsets, removes some register pressure
from romcc)
Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code
in cache_as_ram.inc)
Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with
CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
141 files changed, 456 insertions, 491 deletions
diff --git a/src/Kconfig b/src/Kconfig index 05173ac90c..2eb8cd8203 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -796,10 +796,6 @@ config AP_CODE_IN_CAR bool default n -config USE_INIT - bool - default n - config ENABLE_APIC_EXT_ID bool default n diff --git a/src/arch/i386/lib/console.c b/src/arch/i386/lib/console.c deleted file mode 100644 index 69b5a66f38..0000000000 --- a/src/arch/i386/lib/console.c +++ /dev/null @@ -1,41 +0,0 @@ -#include <build.h> -#include <console/loglevel.h> - -#if CONFIG_USE_PRINTK_IN_CAR == 0 -#include "console_print.c" -#else /* CONFIG_USE_PRINTK_IN_CAR == 1 */ -#include <console/console.h> -#endif /* CONFIG_USE_PRINTK_IN_CAR */ - -void console_init(void) -{ - static const char console_test[] = - "\r\n\r\ncoreboot-" - COREBOOT_VERSION - COREBOOT_EXTRA_VERSION - " " - COREBOOT_BUILD - " starting...\r\n"; - print_info(console_test); -} - - -void post_code(u8 value) -{ -#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0 -#if CONFIG_SERIAL_POST==1 - print_emerg("POST: 0x"); - print_emerg_hex8(value); - print_emerg("\r\n"); -#endif - outb(value, 0x80); -#endif -} - -void die(const char *str) -{ - print_emerg(str); - do { - hlt(); - } while(1); -} diff --git a/src/arch/i386/lib/console_print.c b/src/arch/i386/lib/console_print.c deleted file mode 100644 index 2acec2308a..0000000000 --- a/src/arch/i386/lib/console_print.c +++ /dev/null @@ -1,124 +0,0 @@ -static void __console_tx_byte(unsigned char byte) -{ - uart_tx_byte(byte); -} - -static void __console_tx_nibble(unsigned nibble) -{ - unsigned char digit; - digit = nibble + '0'; - if (digit > '9') { - digit += 39; - } - __console_tx_byte(digit); -} - -static void __console_tx_char(int loglevel, unsigned char byte) -{ - if (ASM_CONSOLE_LOGLEVEL >= loglevel) { - uart_tx_byte(byte); - } -} - -static void __console_tx_hex8(int loglevel, unsigned char value) -{ - if (ASM_CONSOLE_LOGLEVEL >= loglevel) { - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} - -static void __console_tx_hex16(int loglevel, unsigned short value) -{ - if (ASM_CONSOLE_LOGLEVEL >= loglevel) { - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} - -static void __console_tx_hex32(int loglevel, unsigned int value) -{ - if (ASM_CONSOLE_LOGLEVEL >= loglevel) { - __console_tx_nibble((value >> 28U) & 0x0fU); - __console_tx_nibble((value >> 24U) & 0x0fU); - __console_tx_nibble((value >> 20U) & 0x0fU); - __console_tx_nibble((value >> 16U) & 0x0fU); - __console_tx_nibble((value >> 12U) & 0x0fU); - __console_tx_nibble((value >> 8U) & 0x0fU); - __console_tx_nibble((value >> 4U) & 0x0fU); - __console_tx_nibble(value & 0x0fU); - } -} - -static void __console_tx_string(int loglevel, const char *str) -{ - if (ASM_CONSOLE_LOGLEVEL >= loglevel) { - unsigned char ch; - while((ch = *str++) != '\0') { - __console_tx_byte(ch); - } - } -} - -#if defined (__ROMCC__) -#define STATIC -#else -#define STATIC static -#endif - -STATIC void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); } -STATIC void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); } -STATIC void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); } -STATIC void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); } -STATIC void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); } - -STATIC void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); } -STATIC void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); } -STATIC void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); } -STATIC void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); } -STATIC void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); } - -STATIC void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); } -STATIC void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); } -STATIC void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); } -STATIC void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); } -STATIC void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); } - -STATIC void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); } -STATIC void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); } -STATIC void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); } -STATIC void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); } -STATIC void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); } - -STATIC void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); } -STATIC void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); } -STATIC void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); } -STATIC void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); } -STATIC void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); } - -STATIC void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); } -STATIC void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); } -STATIC void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); } -STATIC void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); } -STATIC void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); } - -STATIC void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); } -STATIC void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); } -STATIC void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); } -STATIC void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); } -STATIC void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); } - -STATIC void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); } -STATIC void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); } -STATIC void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); } -STATIC void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); } -STATIC void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); } - -STATIC void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); } -STATIC void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); } -STATIC void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); } -STATIC void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); } -STATIC void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); } - diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index a5dc735369..8de1a7b46a 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -14,3 +14,5 @@ driver-$(CONFIG_CONSOLE_VGA) += vga_console.o driver-$(CONFIG_CONSOLE_BTEXT) += btext_console.o driver-$(CONFIG_CONSOLE_BTEXT) += font-8x16.o driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.o + +$(obj)/console/console.o : $(obj)/build.h diff --git a/src/console/console.c b/src/console/console.c index 4543b0c7b3..ace76d902c 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -2,8 +2,12 @@ * Bootstrap code for the INTEL */ -#include <arch/io.h> #include <console/console.h> +#include <build.h> +#include <arch/hlt.h> + +#ifndef __PRE_RAM__ +#include <arch/io.h> #include <string.h> #include <pc80/mc146818rtc.h> @@ -86,6 +90,42 @@ void post_code(uint8_t value) void __attribute__((noreturn)) die(const char *msg) { printk(BIOS_EMERG, "%s", msg); - post_code(0xff); - while (1); /* Halt */ + //post_code(0xff); + for (;;) + hlt(); /* Halt */ +} + +#else + +void console_init(void) +{ + static const char console_test[] = + "\r\n\r\ncoreboot-" + COREBOOT_VERSION + COREBOOT_EXTRA_VERSION + " " + COREBOOT_BUILD + " starting...\r\n"; + print_info(console_test); +} + +void post_code(u8 value) +{ +#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0 +#if CONFIG_SERIAL_POST==1 + print_emerg("POST: 0x"); + print_emerg_hex8(value); + print_emerg("\r\n"); +#endif + outb(value, 0x80); +#endif } + +void die(const char *str) +{ + print_emerg(str); + do { + hlt(); + } while(1); +} +#endif diff --git a/src/include/console/console.h b/src/include/console/console.h index 851505138d..fe7ea0b1e6 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -33,6 +33,7 @@ extern struct console_driver econsole_drivers[]; extern int console_loglevel; #endif /* !__PRE_RAM__ */ +#ifndef __ROMCC__ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); #undef WE_CLEANED_UP_ALL_SIDE_EFFECTS @@ -40,6 +41,10 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, * disabling cache as ram for a maximum console log level of 6 and above while * it worked fine without. In order to catch such issues reliably we are * always doing a function call to do_printk with the full number of arguments. + * Our favorite reason to do it this way was: + * disable_car(); + * printk(BIOS_DEBUG, "CAR disabled\n"); // oops, garbage stack pointer + * move_stack(); * This slightly increases the code size and some unprinted strings will end * up in the final coreboot binary (most of them compressed). If you want to * avoid this, do a @@ -66,35 +71,35 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, } while(0) #endif -#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) -#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) -#define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) -#define print_err(STR) printk(BIOS_ERR, "%s", (STR)) -#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR)) -#define print_notice(STR) printk(BIOS_NOTICE, "%s", (STR)) -#define print_info(STR) printk(BIOS_INFO, "%s", (STR)) -#define print_debug(STR) printk(BIOS_DEBUG, "%s", (STR)) -#define print_spew(STR) printk(BIOS_SPEW, "%s", (STR)) - -#define print_emerg_char(CH) printk(BIOS_EMERG, "%c", (CH)) -#define print_alert_char(CH) printk(BIOS_ALERT, "%c", (CH)) -#define print_crit_char(CH) printk(BIOS_CRIT, "%c", (CH)) -#define print_err_char(CH) printk(BIOS_ERR, "%c", (CH)) -#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH)) -#define print_notice_char(CH) printk(BIOS_NOTICE, "%c", (CH)) -#define print_info_char(CH) printk(BIOS_INFO, "%c", (CH)) -#define print_debug_char(CH) printk(BIOS_DEBUG, "%c", (CH)) -#define print_spew_char(CH) printk(BIOS_SPEW, "%c", (CH)) - -#define print_emerg_hex8(HEX) printk(BIOS_EMERG, "%02x", (HEX)) -#define print_alert_hex8(HEX) printk(BIOS_ALERT, "%02x", (HEX)) -#define print_crit_hex8(HEX) printk(BIOS_CRIT, "%02x", (HEX)) -#define print_err_hex8(HEX) printk(BIOS_ERR, "%02x", (HEX)) -#define print_warning_hex8(HEX) printk(BIOS_WARNING,"%02x", (HEX)) -#define print_notice_hex8(HEX) printk(BIOS_NOTICE, "%02x", (HEX)) -#define print_info_hex8(HEX) printk(BIOS_INFO, "%02x", (HEX)) -#define print_debug_hex8(HEX) printk(BIOS_DEBUG, "%02x", (HEX)) -#define print_spew_hex8(HEX) printk(BIOS_SPEW, "%02x", (HEX)) +#define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) +#define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) +#define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) +#define print_err(STR) printk(BIOS_ERR, "%s", (STR)) +#define print_warning(STR) printk(BIOS_WARNING,"%s", (STR)) +#define print_notice(STR) printk(BIOS_NOTICE, "%s", (STR)) +#define print_info(STR) printk(BIOS_INFO, "%s", (STR)) +#define print_debug(STR) printk(BIOS_DEBUG, "%s", (STR)) +#define print_spew(STR) printk(BIOS_SPEW, "%s", (STR)) + +#define print_emerg_char(CH) printk(BIOS_EMERG, "%c", (CH)) +#define print_alert_char(CH) printk(BIOS_ALERT, "%c", (CH)) +#define print_crit_char(CH) printk(BIOS_CRIT, "%c", (CH)) +#define print_err_char(CH) printk(BIOS_ERR, "%c", (CH)) +#define print_warning_char(CH) printk(BIOS_WARNING,"%c", (CH)) +#define print_notice_char(CH) printk(BIOS_NOTICE, "%c", (CH)) +#define print_info_char(CH) printk(BIOS_INFO, "%c", (CH)) +#define print_debug_char(CH) printk(BIOS_DEBUG, "%c", (CH)) +#define print_spew_char(CH) printk(BIOS_SPEW, "%c", (CH)) + +#define print_emerg_hex8(HEX) printk(BIOS_EMERG, "%02x", (HEX)) +#define print_alert_hex8(HEX) printk(BIOS_ALERT, "%02x", (HEX)) +#define print_crit_hex8(HEX) printk(BIOS_CRIT, "%02x", (HEX)) +#define print_err_hex8(HEX) printk(BIOS_ERR, "%02x", (HEX)) +#define print_warning_hex8(HEX) printk(BIOS_WARNING,"%02x", (HEX)) +#define print_notice_hex8(HEX) printk(BIOS_NOTICE, "%02x", (HEX)) +#define print_info_hex8(HEX) printk(BIOS_INFO, "%02x", (HEX)) +#define print_debug_hex8(HEX) printk(BIOS_DEBUG, "%02x", (HEX)) +#define print_spew_hex8(HEX) printk(BIOS_SPEW, "%02x", (HEX)) #define print_emerg_hex16(HEX) printk(BIOS_EMERG, "%04x", (HEX)) #define print_alert_hex16(HEX) printk(BIOS_ALERT, "%04x", (HEX)) @@ -115,5 +120,182 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, #define print_info_hex32(HEX) printk(BIOS_INFO, "%08x", (HEX)) #define print_debug_hex32(HEX) printk(BIOS_DEBUG, "%08x", (HEX)) #define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX)) +#else +/* __ROMCC__ */ +static void __console_tx_byte(unsigned char byte) +{ + uart_tx_byte(byte); +} + +static void __console_tx_nibble(unsigned nibble) +{ + unsigned char digit; + digit = nibble + '0'; + if (digit > '9') { + digit += 39; + } + __console_tx_byte(digit); +} + +static void __console_tx_char(int loglevel, unsigned char byte) +{ + if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + uart_tx_byte(byte); + } +} + +static void __console_tx_hex8(int loglevel, unsigned char value) +{ + if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + __console_tx_nibble((value >> 4U) & 0x0fU); + __console_tx_nibble(value & 0x0fU); + } +} + +static void __console_tx_hex16(int loglevel, unsigned short value) +{ + if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + __console_tx_nibble((value >> 12U) & 0x0fU); + __console_tx_nibble((value >> 8U) & 0x0fU); + __console_tx_nibble((value >> 4U) & 0x0fU); + __console_tx_nibble(value & 0x0fU); + } +} + +static void __console_tx_hex32(int loglevel, unsigned int value) +{ + if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + __console_tx_nibble((value >> 28U) & 0x0fU); + __console_tx_nibble((value >> 24U) & 0x0fU); + __console_tx_nibble((value >> 20U) & 0x0fU); + __console_tx_nibble((value >> 16U) & 0x0fU); + __console_tx_nibble((value >> 12U) & 0x0fU); + __console_tx_nibble((value >> 8U) & 0x0fU); + __console_tx_nibble((value >> 4U) & 0x0fU); + __console_tx_nibble(value & 0x0fU); + } +} + +static void __console_tx_string(int loglevel, const char *str) +{ + if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + unsigned char ch; + while((ch = *str++) != '\0') { + if (ch == '\n') + __console_tx_byte('\r'); + __console_tx_byte(ch); + } + } +} + +#define FUNCTIONS_FOR_PRINT +#ifdef FUNCTIONS_FOR_PRINT +static void print_emerg_char(unsigned char byte) { __console_tx_char(BIOS_EMERG, byte); } +static void print_emerg_hex8(unsigned char value){ __console_tx_hex8(BIOS_EMERG, value); } +static void print_emerg_hex16(unsigned short value){ __console_tx_hex16(BIOS_EMERG, value); } +static void print_emerg_hex32(unsigned int value) { __console_tx_hex32(BIOS_EMERG, value); } +static void print_emerg(const char *str) { __console_tx_string(BIOS_EMERG, str); } + +static void print_alert_char(unsigned char byte) { __console_tx_char(BIOS_ALERT, byte); } +static void print_alert_hex8(unsigned char value) { __console_tx_hex8(BIOS_ALERT, value); } +static void print_alert_hex16(unsigned short value){ __console_tx_hex16(BIOS_ALERT, value); } +static void print_alert_hex32(unsigned int value) { __console_tx_hex32(BIOS_ALERT, value); } +static void print_alert(const char *str) { __console_tx_string(BIOS_ALERT, str); } + +static void print_crit_char(unsigned char byte) { __console_tx_char(BIOS_CRIT, byte); } +static void print_crit_hex8(unsigned char value) { __console_tx_hex8(BIOS_CRIT, value); } +static void print_crit_hex16(unsigned short value){ __console_tx_hex16(BIOS_CRIT, value); } +static void print_crit_hex32(unsigned int value) { __console_tx_hex32(BIOS_CRIT, value); } +static void print_crit(const char *str) { __console_tx_string(BIOS_CRIT, str); } + +static void print_err_char(unsigned char byte) { __console_tx_char(BIOS_ERR, byte); } +static void print_err_hex8(unsigned char value) { __console_tx_hex8(BIOS_ERR, value); } +static void print_err_hex16(unsigned short value){ __console_tx_hex16(BIOS_ERR, value); } +static void print_err_hex32(unsigned int value) { __console_tx_hex32(BIOS_ERR, value); } +static void print_err(const char *str) { __console_tx_string(BIOS_ERR, str); } + +static void print_warning_char(unsigned char byte) { __console_tx_char(BIOS_WARNING, byte); } +static void print_warning_hex8(unsigned char value) { __console_tx_hex8(BIOS_WARNING, value); } +static void print_warning_hex16(unsigned short value){ __console_tx_hex16(BIOS_WARNING, value); } +static void print_warning_hex32(unsigned int value) { __console_tx_hex32(BIOS_WARNING, value); } +static void print_warning(const char *str) { __console_tx_string(BIOS_WARNING, str); } + +static void print_notice_char(unsigned char byte) { __console_tx_char(BIOS_NOTICE, byte); } +static void print_notice_hex8(unsigned char value) { __console_tx_hex8(BIOS_NOTICE, value); } +static void print_notice_hex16(unsigned short value){ __console_tx_hex16(BIOS_NOTICE, value); } +static void print_notice_hex32(unsigned int value) { __console_tx_hex32(BIOS_NOTICE, value); } +static void print_notice(const char *str) { __console_tx_string(BIOS_NOTICE, str); } + +static void print_info_char(unsigned char byte) { __console_tx_char(BIOS_INFO, byte); } +static void print_info_hex8(unsigned char value) { __console_tx_hex8(BIOS_INFO, value); } +static void print_info_hex16(unsigned short value){ __console_tx_hex16(BIOS_INFO, value); } +static void print_info_hex32(unsigned int value) { __console_tx_hex32(BIOS_INFO, value); } +static void print_info(const char *str) { __console_tx_string(BIOS_INFO, str); } + +static void print_debug_char(unsigned char byte) { __console_tx_char(BIOS_DEBUG, byte); } +static void print_debug_hex8(unsigned char value) { __console_tx_hex8(BIOS_DEBUG, value); } +static void print_debug_hex16(unsigned short value){ __console_tx_hex16(BIOS_DEBUG, value); } +static void print_debug_hex32(unsigned int value) { __console_tx_hex32(BIOS_DEBUG, value); } +static void print_debug(const char *str) { __console_tx_string(BIOS_DEBUG, str); } + +static void print_spew_char(unsigned char byte) { __console_tx_char(BIOS_SPEW, byte); } +static void print_spew_hex8(unsigned char value) { __console_tx_hex8(BIOS_SPEW, value); } +static void print_spew_hex16(unsigned short value){ __console_tx_hex16(BIOS_SPEW, value); } +static void print_spew_hex32(unsigned int value) { __console_tx_hex32(BIOS_SPEW, value); } +static void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); } + +#else +#define print_emerg(STR) __console_tx_string(BIOS_EMERG, STR) +#define print_alert(STR) __console_tx_string(BIOS_ALERT, STR) +#define print_crit(STR) __console_tx_string(BIOS_CRIT, STR) +#define print_err(STR) __console_tx_string(BIOS_ERR, STR) +#define print_warning(STR) __console_tx_string(BIOS_WARNING, STR) +#define print_notice(STR) __console_tx_string(BIOS_NOTICE, STR) +#define print_info(STR) __console_tx_string(BIOS_INFO, STR) +#define print_debug(STR) __console_tx_string(BIOS_DEBUG, STR) +#define print_spew(STR) __console_tx_string(BIOS_SPEW, STR) + +#define print_emerg_char(CH) __console_tx_char(BIOS_EMERG, CH) +#define print_alert_char(CH) __console_tx_char(BIOS_ALERT, CH) +#define print_crit_char(CH) __console_tx_char(BIOS_CRIT, CH) +#define print_err_char(CH) __console_tx_char(BIOS_ERR, CH) +#define print_warning_char(CH) __console_tx_char(BIOS_WARNING, CH) +#define print_notice_char(CH) __console_tx_char(BIOS_NOTICE, CH) +#define print_info_char(CH) __console_tx_char(BIOS_INFO, CH) +#define print_debug_char(CH) __console_tx_char(BIOS_DEBUG, CH) +#define print_spew_char(CH) __console_tx_char(BIOS_SPEW, CH) + +#define print_emerg_hex8(HEX) __console_tx_hex8(BIOS_EMERG, HEX) +#define print_alert_hex8(HEX) __console_tx_hex8(BIOS_ALERT, HEX) +#define print_crit_hex8(HEX) __console_tx_hex8(BIOS_CRIT, HEX) +#define print_err_hex8(HEX) __console_tx_hex8(BIOS_ERR, HEX) +#define print_warning_hex8(HEX) __console_tx_hex8(BIOS_WARNING, HEX) +#define print_notice_hex8(HEX) __console_tx_hex8(BIOS_NOTICE, HEX) +#define print_info_hex8(HEX) __console_tx_hex8(BIOS_INFO, HEX) +#define print_debug_hex8(HEX) __console_tx_hex8(BIOS_DEBUG, HEX) +#define print_spew_hex8(HEX) __console_tx_hex8(BIOS_SPEW, HEX) + +#define print_emerg_hex16(HEX) __console_tx_hex16(BIOS_EMERG, HEX) +#define print_alert_hex16(HEX) __console_tx_hex16(BIOS_ALERT, HEX) +#define print_crit_hex16(HEX) __console_tx_hex16(BIOS_CRIT, HEX) +#define print_err_hex16(HEX) __console_tx_hex16(BIOS_ERR, HEX) +#define print_warning_hex16(HEX) __console_tx_hex16(BIOS_WARNING, HEX) +#define print_notice_hex16(HEX) __console_tx_hex16(BIOS_NOTICE, HEX) +#define print_info_hex16(HEX) __console_tx_hex16(BIOS_INFO, HEX) +#define print_debug_hex16(HEX) __console_tx_hex16(BIOS_DEBUG, HEX) +#define print_spew_hex16(HEX) __console_tx_hex16(BIOS_SPEW, HEX) + +#define print_emerg_hex32(HEX) __console_tx_hex32(BIOS_EMERG, HEX) +#define print_alert_hex32(HEX) __console_tx_hex32(BIOS_ALERT, HEX) +#define print_crit_hex32(HEX) __console_tx_hex32(BIOS_CRIT, HEX) +#define print_err_hex32(HEX) __console_tx_hex32(BIOS_ERR, HEX) +#define print_warning_hex32(HEX) __console_tx_hex32(BIOS_WARNING, HEX) +#define print_notice_hex32(HEX) __console_tx_hex32(BIOS_NOTICE, HEX) +#define print_info_hex32(HEX) __console_tx_hex32(BIOS_INFO, HEX) +#define print_debug_hex32(HEX) __console_tx_hex32(BIOS_DEBUG, HEX) +#define print_spew_hex32(HEX) __console_tx_hex32(BIOS_SPEW, HEX) +#endif + +#endif #endif /* CONSOLE_CONSOLE_H_ */ diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 4173df22fa..5262972405 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index 25e0b3bbfc..389eea3ac8 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 95ba4b69fd..03ee0f414e 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/advantech/pcm-5820/romstage.c b/src/mainboard/advantech/pcm-5820/romstage.c index 1ee8aadf74..e34d3955c3 100644 --- a/src/mainboard/advantech/pcm-5820/romstage.c +++ b/src/mainboard/advantech/pcm-5820/romstage.c @@ -24,7 +24,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 1547dc4da3..510b8f86f0 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -24,7 +24,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 8decf4c7c2..b46ca394be 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -43,7 +43,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #define post_code(x) outb(x, 0x80) diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index f9ca92fac1..a5991ad1eb 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -43,7 +43,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #define post_code(x) outb(x, 0x80) diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 332e256085..a167228b44 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -47,7 +47,7 @@ #include <cpu/x86/lapic.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "pc80/serial.c" #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 6337e89c2c..8c17b0affa 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -24,7 +24,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index d4dcca3822..f8b64f1320 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -37,7 +37,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #define post_code(x) outb(x, 0x80) diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index 087fe1842a..e9b21ed029 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -5,7 +5,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c index 4b8e2fe06d..582e93abc2 100644 --- a/src/mainboard/amd/serengeti_cheetah/ap_romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/ap_romstage.c @@ -23,25 +23,10 @@ #include "pc80/serial.c" #include "./arch/i386/lib/printk_init.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/uart8250.c" #include "console/vtxprintf.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 247e920b95..c46bdf447d 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -40,7 +40,7 @@ static void post_code(uint8_t value) { } #endif #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 4d86535bbe..d7b6c63c0e 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -47,7 +47,7 @@ #include <cpu/x86/lapic.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "pc80/serial.c" #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 975d259d49..3440e717c0 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index d55330274d..2172338685 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/asi/mb_5blgp/romstage.c b/src/mainboard/asi/mb_5blgp/romstage.c index 427911260a..3ee9241d54 100644 --- a/src/mainboard/asi/mb_5blgp/romstage.c +++ b/src/mainboard/asi/mb_5blgp/romstage.c @@ -24,7 +24,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/asi/mb_5blmp/romstage.c b/src/mainboard/asi/mb_5blmp/romstage.c index d4d3be9d1d..693e440934 100644 --- a/src/mainboard/asi/mb_5blmp/romstage.c +++ b/src/mainboard/asi/mb_5blmp/romstage.c @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc87351/pc87351_early_serial.c" diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 61e6b5450c..b64ccae0fd 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -49,7 +49,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 7e9b6fc4dd..c2390c76d1 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -47,7 +47,7 @@ unsigned int get_sbdn(unsigned bus); #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 81971914ce..2514019aa6 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -52,7 +52,7 @@ unsigned int get_sbdn(unsigned bus); #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index 2345346353..223201971c 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index 82076e546f..22fa410e33 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" #include "northbridge/intel/i82810/raminit.h" diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index 3ccd8ec096..1056360a9e 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -27,7 +27,7 @@ #include <stdlib.h> #include <cpu/x86/lapic.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 676c8e27e1..6e44048653 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -27,7 +27,7 @@ #include <stdlib.h> #include <cpu/x86/lapic.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index eeb46e0a01..8974174dec 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index 44cfb2ca82..462df70151 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index dbee44d893..2445b503c5 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 671bde17d4..5da8dbf5ca 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/axus/tc320/romstage.c b/src/mainboard/axus/tc320/romstage.c index 0e828fe996..4a6cc25a10 100644 --- a/src/mainboard/axus/tc320/romstage.c +++ b/src/mainboard/axus/tc320/romstage.c @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index dc960d8cee..e7ed478879 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/bcom/winnet100/romstage.c b/src/mainboard/bcom/winnet100/romstage.c index 07f5ad5a92..744623f84a 100644 --- a/src/mainboard/bcom/winnet100/romstage.c +++ b/src/mainboard/bcom/winnet100/romstage.c @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 90de05a1f6..2801f9e06a 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index 525e2c561c..69f07f351b 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index d67b713451..71211c587c 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -14,7 +14,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #if 0 diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index 1d9826dd7b..fbc195ab65 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/dell/s1850/romstage.c b/src/mainboard/dell/s1850/romstage.c index 37b28aace6..17a4113afd 100644 --- a/src/mainboard/dell/s1850/romstage.c +++ b/src/mainboard/dell/s1850/romstage.c @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" @@ -170,10 +170,12 @@ static void main(unsigned long bist) static const struct mem_controller mch[] = { { .node_id = 0, + /* .f0 = PCI_DEV(0, 0x00, 0), .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + */ /* the wiring on this part is really messed up */ /* this is my best guess so far */ .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, }, diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 1e0a8dcc47..6bd7068a8a 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -12,7 +12,7 @@ #include <stdlib.h> #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c index 8db527d52b..4865622181 100644 --- a/src/mainboard/digitallogic/msm586seg/romstage.c +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -7,7 +7,7 @@ #include <arch/hlt.h> #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" //#include "lib/delay.c" diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 9d5d431f39..1983b9678f 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -5,7 +5,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/eaglelion/5bcm/romstage.c b/src/mainboard/eaglelion/5bcm/romstage.c index 6fa43e3fe3..633c23cd5a 100644 --- a/src/mainboard/eaglelion/5bcm/romstage.c +++ b/src/mainboard/eaglelion/5bcm/romstage.c @@ -6,7 +6,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" //#include "southbridge/intel/i440bx/i440bx_early_smbus.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" diff --git a/src/mainboard/emulation/qemu-x86/romstage.c b/src/mainboard/emulation/qemu-x86/romstage.c index 02d7350626..1d6eeded11 100644 --- a/src/mainboard/emulation/qemu-x86/romstage.c +++ b/src/mainboard/emulation/qemu-x86/romstage.c @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index d5c671fdd5..721b20806a 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c index 452084f7c4..d0a5eeb351 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c @@ -45,22 +45,10 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" - -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif +#include "lib/uart8250.c" +#include "arch/i386/lib/printk_init.c" +#include "console/vtxprintf.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index f55ee1b789..d66bf51f59 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -54,7 +54,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/sis/sis966/sis966_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" diff --git a/src/mainboard/gigabyte/m57sli/ap_romstage.c b/src/mainboard/gigabyte/m57sli/ap_romstage.c index 007dfa9a95..2bd3205842 100644 --- a/src/mainboard/gigabyte/m57sli/ap_romstage.c +++ b/src/mainboard/gigabyte/m57sli/ap_romstage.c @@ -43,22 +43,10 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" - -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif +#include "lib/uart8250.c" +#include "arch/i386/lib/printk_init.c" +#include "console/vtxprintf.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index a03e839d6f..9ac67e465f 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -52,7 +52,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 6b617afdfa..c70ff27556 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -58,7 +58,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index ac8d8b8a84..6757d76aef 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" /* TODO: It's a PC87364 actually! */ #include "superio/nsc/pc87360/pc87360_early_serial.c" diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index a9dccf0dcf..ab42a7ef9d 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 1843a8fbba..9bbad71346 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c index f4a40e8b76..7b2dfb8bf9 100644 --- a/src/mainboard/iei/juki-511p/romstage.c +++ b/src/mainboard/iei/juki-511p/romstage.c @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83977f/w83977f_early_serial.c" #include "southbridge/amd/cs5530/cs5530_enable_rom.c" diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c index e25b889e3b..0873450b9d 100644 --- a/src/mainboard/iei/nova4899r/romstage.c +++ b/src/mainboard/iei/nova4899r/romstage.c @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" #include "southbridge/amd/cs5530/cs5530_enable_rom.c" diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index 3f2435d69b..80226a940d 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -24,7 +24,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 48f3f78e7b..7767b1cc47 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -38,7 +38,7 @@ #include <console/console.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/x86/bist.h> #if CONFIG_USBDEBUG_DIRECT diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 7eb83c9153..13c7e951f3 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,7 +33,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/x86/bist.h> #include "lib/ramtest.c" diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c index 04b552fb25..4255e43c21 100644 --- a/src/mainboard/intel/jarrell/romstage.c +++ b/src/mainboard/intel/jarrell/romstage.c @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" @@ -60,10 +60,12 @@ static void main(unsigned long bist) static const struct mem_controller mch[] = { { .node_id = 0, + /* .f0 = PCI_DEV(0, 0x00, 0), .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + */ .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 }, .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 }, } diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index f23169736b..ed8e647c53 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -28,7 +28,7 @@ #include <cpu/x86/lapic.h> #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index b2e04be896..4163c873b0 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -29,7 +29,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "pc80/udelay_io.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c index 240e917964..685f3b8700 100644 --- a/src/mainboard/intel/xe7501devkit/romstage.c +++ b/src/mainboard/intel/xe7501devkit/romstage.c @@ -9,7 +9,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 1f865adf0c..fec1020dba 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -30,7 +30,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 55ba27a09c..3ceef39900 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -30,7 +30,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 55ba27a09c..3ceef39900 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -30,7 +30,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c index ac3ab97f91..4de5aa72ab 100644 --- a/src/mainboard/jetway/j7f24/romstage.c +++ b/src/mainboard/jetway/j7f24/romstage.c @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 121eb143f0..247b5eb9af 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -47,7 +47,7 @@ #include <console/console.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/x86/bist.h> #if CONFIG_USBDEBUG_DIRECT diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 28df9b74bc..200f7567bc 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -44,7 +44,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #define post_code(x) outb(x, 0x80) diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index c5ed73aec6..bc097e385d 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -5,7 +5,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 3884d28c86..67f4c3c381 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -28,7 +28,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index e92cf7adc7..7a73a1b402 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -29,7 +29,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index d06bfdd11a..7a532e0fd5 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index f061cb5460..2bf27e3e8d 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index b250994939..2a6dce7beb 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index e5a6bf9fe4..71f5de1325 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -26,7 +26,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index 4a558eba6c..a1096a4011 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/intel/i82810/raminit.h" diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 80f217c363..2a6c6f368b 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -51,7 +51,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" diff --git a/src/mainboard/msi/ms7260/ap_romstage.c b/src/mainboard/msi/ms7260/ap_romstage.c index 84ba6c1daf..f8ac2fec3a 100644 --- a/src/mainboard/msi/ms7260/ap_romstage.c +++ b/src/mainboard/msi/ms7260/ap_romstage.c @@ -39,10 +39,8 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif -#include "arch/i386/lib/console.c" + +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 9016075fb9..7e97a27e53 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -56,7 +56,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index cf625e5561..350980e5d2 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -50,7 +50,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if 0 static void post_code(uint8_t value) { diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 270924392a..24a307eff6 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -45,7 +45,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index e11b4382e5..622dfd1058 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -46,7 +46,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index 9f03a6e594..33b04d983f 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82810/raminit.h" diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 7ee9d1600a..f6d2e54dc6 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -15,7 +15,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #if 0 diff --git a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c index 1a9121e40f..0935df23ad 100644 --- a/src/mainboard/nvidia/l1_2pvv/ap_romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/ap_romstage.c @@ -43,22 +43,10 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" - -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif +#include "lib/uart8250.c" +#include "arch/i386/lib/printk_init.c" +#include "console/vtxprintf.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index daaf84550d..cf4501f460 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -52,7 +52,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" diff --git a/src/mainboard/olpc/btest/romstage.c b/src/mainboard/olpc/btest/romstage.c index c47ed79594..b13700da44 100644 --- a/src/mainboard/olpc/btest/romstage.c +++ b/src/mainboard/olpc/btest/romstage.c @@ -5,7 +5,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/olpc/rev_a/romstage.c b/src/mainboard/olpc/rev_a/romstage.c index c47ed79594..b13700da44 100644 --- a/src/mainboard/olpc/rev_a/romstage.c +++ b/src/mainboard/olpc/rev_a/romstage.c @@ -5,7 +5,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 764400c98a..07f11ff647 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index a7635ee8ac..b1bc4b4d1a 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -27,7 +27,7 @@ #include <arch/hlt.h> #include "pc80/serial.c" #include "pc80/udelay_io.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 3a2c672b51..28f56a89f3 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -40,7 +40,7 @@ #include <console/console.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/x86/bist.h> #if CONFIG_USBDEBUG_DIRECT diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index cbf4bd3ea0..1636c42f86 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index e006a74680..84e29b8e9f 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -17,7 +17,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/supermicro/h8dme/ap_romstage.c b/src/mainboard/supermicro/h8dme/ap_romstage.c index bb625933e7..05c62c3e2c 100644 --- a/src/mainboard/supermicro/h8dme/ap_romstage.c +++ b/src/mainboard/supermicro/h8dme/ap_romstage.c @@ -43,26 +43,11 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/uart8250.c" #include "console/vtxprintf.c" #include "./arch/i386/lib/printk_init.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index a9c3ef4afa..2edf58c39d 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -50,7 +50,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/supermicro/h8dmr/ap_romstage.c b/src/mainboard/supermicro/h8dmr/ap_romstage.c index bb625933e7..05c62c3e2c 100644 --- a/src/mainboard/supermicro/h8dmr/ap_romstage.c +++ b/src/mainboard/supermicro/h8dmr/ap_romstage.c @@ -43,26 +43,11 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/uart8250.c" #include "console/vtxprintf.c" #include "./arch/i386/lib/printk_init.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 552098d230..a56f799c7a 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -53,7 +53,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 068e27f16d..095c4b1f1f 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -47,7 +47,7 @@ // for enable the FAN #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index a65fd34456..3c4dedefaf 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -48,7 +48,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> diff --git a/src/mainboard/supermicro/x6dai_g/romstage.c b/src/mainboard/supermicro/x6dai_g/romstage.c index 0b274c1947..330b7ce8a7 100644 --- a/src/mainboard/supermicro/x6dai_g/romstage.c +++ b/src/mainboard/supermicro/x6dai_g/romstage.c @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" #include "northbridge/intel/e7525/raminit.h" diff --git a/src/mainboard/supermicro/x6dhe_g/romstage.c b/src/mainboard/supermicro/x6dhe_g/romstage.c index 5cbb83074e..58168e646c 100644 --- a/src/mainboard/supermicro/x6dhe_g/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g/romstage.c @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" @@ -62,10 +62,12 @@ static void main(unsigned long bist) static const struct mem_controller mch[] = { { .node_id = 0, + /* .f0 = PCI_DEV(0, 0x00, 0), .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + */ .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, }, .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, }, } diff --git a/src/mainboard/supermicro/x6dhe_g2/romstage.c b/src/mainboard/supermicro/x6dhe_g2/romstage.c index 4af2a54131..46b1ca54ce 100644 --- a/src/mainboard/supermicro/x6dhe_g2/romstage.c +++ b/src/mainboard/supermicro/x6dhe_g2/romstage.c @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" @@ -62,10 +62,12 @@ static void main(unsigned long bist) static const struct mem_controller mch[] = { { .node_id = 0, + /* .f0 = PCI_DEV(0, 0x00, 0), .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + */ .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, diff --git a/src/mainboard/supermicro/x6dhr_ig/romstage.c b/src/mainboard/supermicro/x6dhr_ig/romstage.c index 7ddb2c46d7..a703d15277 100644 --- a/src/mainboard/supermicro/x6dhr_ig/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig/romstage.c @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" @@ -63,10 +63,12 @@ static void main(unsigned long bist) static const struct mem_controller mch[] = { { .node_id = 0, + /* .f0 = PCI_DEV(0, 0x00, 0), .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + */ .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, } diff --git a/src/mainboard/supermicro/x6dhr_ig2/romstage.c b/src/mainboard/supermicro/x6dhr_ig2/romstage.c index 38c06d5000..3b46b31007 100644 --- a/src/mainboard/supermicro/x6dhr_ig2/romstage.c +++ b/src/mainboard/supermicro/x6dhr_ig2/romstage.c @@ -8,7 +8,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" @@ -63,10 +63,12 @@ static void main(unsigned long bist) static const struct mem_controller mch[] = { { .node_id = 0, + /* .f0 = PCI_DEV(0, 0x00, 0), .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), + */ .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, } diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 309016e787..4f4cb1505f 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -43,7 +43,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #define post_code(x) outb(x, 0x80) diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 769f674a91..1fba17f88b 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -43,7 +43,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #define post_code(x) outb(x, 0x80) diff --git a/src/mainboard/technologic/ts5300/romstage.c b/src/mainboard/technologic/ts5300/romstage.c index b5db71d3eb..7fd5423c5d 100644 --- a/src/mainboard/technologic/ts5300/romstage.c +++ b/src/mainboard/technologic/ts5300/romstage.c @@ -13,7 +13,7 @@ #include <arch/hlt.h> #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/televideo/tc7020/romstage.c b/src/mainboard/televideo/tc7020/romstage.c index 07f5ad5a92..744623f84a 100644 --- a/src/mainboard/televideo/tc7020/romstage.c +++ b/src/mainboard/televideo/tc7020/romstage.c @@ -25,7 +25,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index 50a6335fb4..4a8e0a698a 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -28,7 +28,7 @@ #include <arch/llshell.h> #include "pc80/serial.c" #include "pc80/udelay_io.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i82830/raminit.h" diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index 6c1ba5891a..893eca59af 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -26,7 +26,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 8ca9c5cba5..74d043b04a 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -9,20 +9,9 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" @@ -139,7 +128,7 @@ void amd64_main(unsigned long bist) "movl %%esp, %0\n\t" : "=a" (v_esp) ); -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); #else print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n"); @@ -151,7 +140,7 @@ void amd64_main(unsigned long bist) cpu_reset_x: -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "cpu_reset = %08x\r\n",cpu_reset); #else print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n"); @@ -200,7 +189,7 @@ cpu_reset_x: { print_debug("Use Ram as Stack now - \r\n"); } -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); #else print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n"); diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 22eecc9ec9..3dfc851460 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #if 0 diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index e57c3642b5..ee5c659ad8 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 2dbcdbebf1..13e5305eea 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index b47bf584e8..50593b83bf 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -14,7 +14,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #if 0 diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index d801abbdc9..41da91c842 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index a6e4f8e2cc..470b3e384a 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -9,7 +9,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #if 0 diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index 838c71c316..149c0c84fb 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -15,7 +15,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 099c29aa36..111b5b5fc5 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -15,7 +15,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index 98ac94c3e1..a52af343e6 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -17,7 +17,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/tyan/s2912/ap_romstage.c b/src/mainboard/tyan/s2912/ap_romstage.c index 3e98a5c979..7c9b43862c 100644 --- a/src/mainboard/tyan/s2912/ap_romstage.c +++ b/src/mainboard/tyan/s2912/ap_romstage.c @@ -43,11 +43,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - -#include "arch/i386/lib/console.c" +#include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 0db72dff24..0a07dfede8 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -52,7 +52,7 @@ #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 9081945511..5c72639d5e 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -46,7 +46,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #if CONFIG_USBDEBUG_DIRECT #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c" #include "pc80/usbdebug_direct_serial.c" diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 804531b0cd..430e547164 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -10,7 +10,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 6dd2b042b0..11c36cb698 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -9,7 +9,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 1c4969c322..960a738b6d 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c index 9dcb4a8939..2d741a1246 100644 --- a/src/mainboard/via/epia-m/romstage.c +++ b/src/mainboard/via/epia-m/romstage.c @@ -10,7 +10,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/vt8623/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 451a7ba7e1..80de0afc71 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -33,16 +33,14 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/vx800/vx800.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 #include <string.h> -#endif #include "cpu/x86/lapic/boot_cpu.c" /* This file contains the board-special SI value for raminit.c. */ @@ -726,7 +724,7 @@ void amd64_main(unsigned long bist) */ unsigned v_esp; __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)); -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); #else print_debug("v_esp="); @@ -745,7 +743,7 @@ cpu_reset_x: */ cpu_reset = 0; -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset); #else print_debug("cpu_reset = "); @@ -795,7 +793,7 @@ cpu_reset_x: else print_debug("Use Ram as Stack now - \r\n"); -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); #else print_debug("new_cpu_reset = "); diff --git a/src/mainboard/via/epia-n/romstage.c b/src/mainboard/via/epia-n/romstage.c index 5f3ebc3210..9819048a25 100644 --- a/src/mainboard/via/epia-n/romstage.c +++ b/src/mainboard/via/epia-n/romstage.c @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cn400/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" diff --git a/src/mainboard/via/epia/romstage.c b/src/mainboard/via/epia/romstage.c index 1b5e9e21b8..301556ddaf 100644 --- a/src/mainboard/via/epia/romstage.c +++ b/src/mainboard/via/epia/romstage.c @@ -6,7 +6,7 @@ #include <arch/hlt.h> #include <stdlib.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/vt8601/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 9bfaefffc4..71ad25908a 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -28,7 +28,7 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cn700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index 168e496f22..719a3581e6 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -27,7 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cx700/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index fecbe486d1..5a8e94bde4 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -25,7 +25,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c index bfe1103207..329c1afb83 100644 --- a/src/northbridge/amd/amdk8/raminit_test.c +++ b/src/northbridge/amd/amdk8/raminit_test.c @@ -124,7 +124,7 @@ static void hlt(void) { longjmp(end_buf, 2); } -#include "../../../arch/i386/lib/console.c" +#include "console/console.c" unsigned long log2(unsigned long x) { diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c index bb4ebbdfe3..3965addcb2 100644 --- a/src/northbridge/intel/e7520/raminit.c +++ b/src/northbridge/intel/e7520/raminit.c @@ -67,7 +67,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) device_t dev; unsigned where; unsigned long reg; - dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0; + dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + PCI_DEV(0, 0x00, 0); where = register_values[i] & 0xff; reg = pci_read_config32(dev, where); reg &= register_values[i+1]; @@ -181,27 +181,27 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, long dimm_mask) sz.side1 -= 29; cum += (1 << sz.side1); /* DRB = 0x60 */ - pci_write_config8(ctrl->f0, DRB + (i*2), cum); + pci_write_config8(PCI_DEV(0, 0x00, 0), DRB + (i*2), cum); if( sz.side2 > 28) { sz.side2 -= 29; cum += (1 << sz.side2); } - pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum); + pci_write_config8(PCI_DEV(0, 0x00, 0), DRB+1 + (i*2), cum); } else { - pci_write_config8(ctrl->f0, DRB + (i*2), cum); - pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum); + pci_write_config8(PCI_DEV(0, 0x00, 0), DRB + (i*2), cum); + pci_write_config8(PCI_DEV(0, 0x00, 0), DRB+1 + (i*2), cum); } } /* set TOM top of memory 0xcc */ - pci_write_config16(ctrl->f0, TOM, cum); + pci_write_config16(PCI_DEV(0, 0x00, 0), TOM, cum); /* set TOLM top of low memory */ if(cum > 0x18) { cum = 0x18; } cum <<= 11; /* 0xc4 TOLM */ - pci_write_config16(ctrl->f0, TOLM, cum); + pci_write_config16(PCI_DEV(0, 0x00, 0), TOLM, cum); return 0; } @@ -279,7 +279,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl, } /* 0x70 DRA */ - pci_write_config32(ctrl->f0, DRA, dra); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRA, dra); goto out; val_err: @@ -309,7 +309,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, static const int latency_indicies[] = { 26, 23, 9 }; /* 0x78 DRT */ - drt = pci_read_config32(ctrl->f0, DRT); + drt = pci_read_config32(PCI_DEV(0, 0x00, 0), DRT); drt &= 3; /* save bits 1:0 */ for(first_dimm = 0; first_dimm < 4; first_dimm++) { @@ -542,7 +542,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl, } /* 0x78 DRT */ - pci_write_config32(ctrl->f0, DRT, drt); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRT, drt); return(cas_latency); } @@ -563,7 +563,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl, static const unsigned char fsb_conversion[4] = {3,1,3,2}; /* 0x7c DRC */ - drc = pci_read_config32(ctrl->f0, DRC); + drc = pci_read_config32(PCI_DEV(0, 0x00, 0), DRC); for(cnt=0; cnt < 4; cnt++) { if (!(dimm_mask & (1 << cnt))) { continue; @@ -727,12 +727,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) /* Set up northbridge values */ /* ODT enable */ - pci_write_config32(ctrl->f0, 0x88, 0xf0000180); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xf0000180); /* Figure out which slots are Empty, Single, or Double sided */ for(i=0,t4=0,c2=0;i<8;i+=2) { - c1 = pci_read_config8(ctrl->f0, DRB+i); + c1 = pci_read_config8(PCI_DEV(0, 0x00, 0), DRB+i); if(c1 == c2) continue; - c2 = pci_read_config8(ctrl->f0, DRB+1+i); + c2 = pci_read_config8(PCI_DEV(0, 0x00, 0), DRB+1+i); if(c1 == c2) t4 |= (1 << (i*4)); else @@ -778,7 +778,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) print_debug_hex32(data32); print_debug("\r\n"); - pci_write_config32(ctrl->f0, 0xb0, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0xb0, data32); for(dimm=0;dimm<8;dimm+=1) { @@ -1079,10 +1079,10 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* 0x80 */ #ifdef DIMM_MAP_LOGICAL - pci_write_config32(ctrl->f0, DRM, + pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, 0x00210000 | DIMM_MAP_LOGICAL); #else - pci_write_config32(ctrl->f0, DRM, 0x00211248); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, 0x00211248); #endif /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); @@ -1097,20 +1097,20 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* drc bits 1:0 = DIMM speed, bits 3:2 = FSB speed */ for(iptr = gearing[(drc&3)+((((drc>>2)&3)-1)*3)].clkgr,cnt=0; cnt<4;cnt++) { - pci_write_config32(ctrl->f0, 0xa0+(cnt*4), iptr[cnt]); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0xa0+(cnt*4), iptr[cnt]); } /* 0x7c DRC */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); /* turn the clocks on */ /* 0x8c CKDIS */ - pci_write_config16(ctrl->f0, CKDIS, 0x0000); + pci_write_config16(PCI_DEV(0, 0x00, 0), CKDIS, 0x0000); /* 0x9a DDRCSR Take subsystem out of idle */ - data16 = pci_read_config16(ctrl->f0, DDRCSR); + data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DDRCSR); data16 &= ~(7 << 12); data16 |= (3 << 12); /* use dual channel lock step */ - pci_write_config16(ctrl->f0, DDRCSR, data16); + pci_write_config16(PCI_DEV(0, 0x00, 0), DDRCSR, data16); /* program row size DRB */ spd_set_ram_size(ctrl, mask); @@ -1287,23 +1287,23 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) set_on_dimm_termination_enable(ctrl); } else { /* ddr */ - pci_write_config32(ctrl->f0, 0x88, 0xa0000000 ); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x88, 0xa0000000 ); } /* receive enable calibration */ set_receive_enable(ctrl); /* DQS */ - pci_write_config32(ctrl->f0, 0x94, 0x3904a100 ); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 ); for(i = 0, cnt = (BAR+0x200); i < 24; i++, cnt+=4) { write32(cnt, dqs_data[i]); } - pci_write_config32(ctrl->f0, 0x94, 0x3904a100 ); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x94, 0x3904a100 ); /* Enable refresh */ /* 0x7c DRC */ data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); write32(BAR+DCALCSR, 0x0008000f); /* clear memory and init ECC */ @@ -1320,13 +1320,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) } /* Bring memory subsystem on line */ - data32 = pci_read_config32(ctrl->f0, 0x98); + data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98); data32 |= (1 << 31); - pci_write_config32(ctrl->f0, 0x98, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0x98, data32); /* wait for completion */ print_debug("Waiting for mem complete\r\n"); while(1) { - data32 = pci_read_config32(ctrl->f0, 0x98); + data32 = pci_read_config32(PCI_DEV(0, 0x00, 0), 0x98); if( (data32 & (1<<31)) == 0) break; } @@ -1336,17 +1336,17 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* 0x7c DRC */ drc |= (1 << 29); data32 = drc & ~(3 << 20); /* clear ECC mode */ - pci_write_config32(ctrl->f0, DRC, data32); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, data32); /* Set the ecc mode */ - pci_write_config32(ctrl->f0, DRC, drc); + pci_write_config32(PCI_DEV(0, 0x00, 0), DRC, drc); /* Enable memory scrubbing */ /* 0x52 MCHSCRB */ - data16 = pci_read_config16(ctrl->f0, MCHSCRB); + data16 = pci_read_config16(PCI_DEV(0, 0x00, 0), MCHSCRB); data16 &= ~0x0f; data16 |= ((2 << 2) | (2 << 0)); - pci_write_config16(ctrl->f0, MCHSCRB, data16); + pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16); /* The memory is now setup, use it */ cache_lbmem(MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/e7520/raminit.h b/src/northbridge/intel/e7520/raminit.h index 183ace8385..9fcc3801bb 100644 --- a/src/northbridge/intel/e7520/raminit.h +++ b/src/northbridge/intel/e7520/raminit.h @@ -4,9 +4,9 @@ #define DIMM_SOCKETS 4 struct mem_controller { unsigned node_id; - device_t f0, f1, f2, f3; - uint16_t channel0[DIMM_SOCKETS]; - uint16_t channel1[DIMM_SOCKETS]; + // device_t f0, f1, f2, f3; + u16 channel0[DIMM_SOCKETS]; + u16 channel1[DIMM_SOCKETS]; }; #endif /* RAMINIT_H */ diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c index c7efb51791..80ee22c22a 100644 --- a/src/northbridge/via/vx800/examples/romstage.c +++ b/src/northbridge/via/vx800/examples/romstage.c @@ -31,16 +31,14 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include "pc80/serial.c" -#include "arch/i386/lib/console.c" +#include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/vx800/vx800.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 #include "lib/memcpy.c" -#endif #include "cpu/x86/lapic/boot_cpu.c" #include "driving_clk_phase_data.c" @@ -573,7 +571,7 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav unsigned v_esp; __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp) ); -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "v_esp=%08x\r\n", v_esp); #else print_debug("v_esp="); @@ -589,7 +587,7 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav // it seems that cpu_reset is not used before this, so I just reset it, (this is because the s3 resume, setting in mtrr and copy data may destroy //stack cpu_reset = 0; -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "cpu_reset = %08x\r\n", cpu_reset); #else print_debug("cpu_reset = "); @@ -641,7 +639,7 @@ So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c hav } else { print_debug("Use Ram as Stack now - \r\n"); } -#if CONFIG_USE_INIT +#if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "new_cpu_reset = %08x\r\n", new_cpu_reset); #else print_debug("new_cpu_reset = "); |