Revert "sandy/ivybridge: use LAPIC timer in SMM"

This reverts commit a3aa8da2acec28670b724b7897ae054592746674.

Chrome OS builds require the monotonic timer API in SMM for ELOG_GSMI,
but sandy/ivy doesn't provide it. The commit tried to work around that
by using generic LAPIC code instead, but this leads to multiple
definition errors in other configurations (and it may be unreliable once
the OS reconfigured the APIC timers anyhow).

This fixes the situation for the non-ELOG_GSMI case (which is more or
less everybody but Chrome OS). ELOG_GSMI requires a separate fix.

Change-Id: If4d69a122b020e5b2d2316b8da225435f6b2bef0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10811
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

3 files changed, 56 insertions, 3 deletions

diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index baa8292d30..3061024f39 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -3,8 +3,5 @@ ramstage-y += lapic_cpu_init.c
 ramstage-y += secondary.S
 romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
-ifeq ($(CONFIG_LAPIC_MONOTONIC_TIMER),y)
-smm-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
-endif
 romstage-y += boot_cpu.c
 ramstage-y += boot_cpu.c
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 60765f2da1..cf79459df2 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -42,6 +42,7 @@ romstage-y += early_init.c
 romstage-y += report_platform.c
 romstage-y += ../../../arch/x86/lib/walkcbfs.S
 
+smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 
 # We don't ship that, but booting without it is bound to fail
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
new file mode 100644
index 0000000000..b150253247
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/udelay.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+
+/**
+ * Intel Sandy Bridge/Ivy Bridge CPUs always run the TSC at BCLK=100MHz
+ */
+
+void udelay(u32 us)
+{
+	u32 dword;
+	tsc_t tsc, tsc1, tscd;
+	msr_t msr;
+	u32 fsb = 100, divisor;
+	u32 d;			/* ticks per us */
+
+	msr = rdmsr(0xce);
+	divisor = (msr.lo >> 8) & 0xff;
+
+	d = fsb * divisor;	/* On Core/Core2 this is divided by 4 */
+	multiply_to_tsc(&tscd, us, d);
+
+	tsc1 = rdtsc();
+	dword = tsc1.lo + tscd.lo;
+	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+		tsc1.hi++;
+	}
+	tsc1.lo = dword;
+	tsc1.hi += tscd.hi;
+
+	do {
+		tsc = rdtsc();
+	} while ((tsc.hi < tsc1.hi)
+		 || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
+}