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authorAngel Pons <th3fanbus@gmail.com>2020-07-07 18:15:47 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-25 10:22:41 +0000
commit5bcd35d6a5266d8894168ff24de6c23c751f0b14 (patch)
treea1e25de42cb8deeed4460f97ac08d39e0198c469 /src
parent1fb17d65cfa0877577239767757ae27d2625d74c (diff)
downloadcoreboot-5bcd35d6a5266d8894168ff24de6c23c751f0b14.tar.xz
soc/intel/baytrail/smihandler.c: Align with Braswell
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: Iaa6d5d72cd0368342205a9b98552c1e0762abbce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43198 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/baytrail/smihandler.c19
1 files changed, 7 insertions, 12 deletions
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 57e8583675..6f3f07e73d 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -68,8 +68,7 @@ static void busmaster_disable_on_bus(int bus)
/* If this is a bridge, then follow it. */
hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
+ if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) {
unsigned int buses;
buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
busmaster_disable_on_bus((buses >> 8) & 0xff);
@@ -191,18 +190,17 @@ static void southbridge_smi_gsmi(void)
{
u32 *ret, *param;
uint8_t sub_command;
- em64t100_smm_state_save_area_t *io_smi =
- smi_apmc_find_state_save(APM_CNT_ELOG_GSMI);
+ em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI);
if (!io_smi)
return;
/* Command and return value in EAX */
- ret = (u32*)&io_smi->rax;
+ ret = (u32 *)&io_smi->rax;
sub_command = (uint8_t)(*ret >> 8);
/* Parameter buffer in EBX */
- param = (u32*)&io_smi->rbx;
+ param = (u32 *)&io_smi->rbx;
/* drivers/elog/gsmi.c */
*ret = gsmi_exec(sub_command, param);
@@ -265,8 +263,7 @@ static void soc_legacy(void)
static void southbridge_smi_store(void)
{
u8 sub_command, ret;
- em64t100_smm_state_save_area_t *io_smi =
- smi_apmc_find_state_save(APM_CNT_SMMSTORE);
+ em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE);
uint32_t reg_ebx;
if (!io_smi)
@@ -317,8 +314,7 @@ static void southbridge_smi_apmc(void)
break;
case APM_CNT_GNVS_UPDATE:
if (smm_initialized) {
- printk(BIOS_DEBUG,
- "SMI#: SMM structures already initialized!\n");
+ printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
return;
}
state = smi_apmc_find_state_save(reg8);
@@ -447,8 +443,7 @@ void southbridge_smi_handler(void)
southbridge_smi[i]();
} else {
printk(BIOS_DEBUG,
- "SMI_STS[%d] occurred, but no "
- "handler available.\n", i);
+ "SMI_STS[%d] occurred, but no handler available.\n", i);
}
}