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authorBora Guvendik <bora.guvendik@intel.com>2017-09-25 14:33:17 -0700
committerAaron Durbin <adurbin@chromium.org>2017-10-03 20:24:35 +0000
commit5d11cc9d7e0ee016d6b6c540d010b212291d61cd (patch)
tree14c4b55ae277934b61d580c71f9917695ad4fdf0 /src
parent747f05675ecf2d0fa4635c3b25e5726f7fe7d98d (diff)
downloadcoreboot-5d11cc9d7e0ee016d6b6c540d010b212291d61cd.tar.xz
soc/intel/cannonlake: add initial ASL methods for SCS, GPIO
Add ACPI methods for gpio, scs and pcr. TEST=Boot to OS. Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21685 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/cannonlake/acpi/gpio.asl102
-rw-r--r--src/soc/intel/cannonlake/acpi/pcr.asl23
-rw-r--r--src/soc/intel/cannonlake/acpi/scs.asl24
-rw-r--r--src/soc/intel/cannonlake/acpi/southbridge.asl9
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_defs.h2
5 files changed, 160 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl
new file mode 100644
index 0000000000..ae3ef5b0b7
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/gpio.asl
@@ -0,0 +1,102 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <soc/gpio_defs.h>
+#include <soc/irq.h>
+#include <soc/pcr_ids.h>
+
+
+Device (GPIO)
+{
+ Name (_HID, "INT34BB")
+ Name (_UID, 0)
+ Name (_DDN, "GPIO Controller")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, 0, COM0)
+ Memory32Fixed (ReadWrite, 0, 0, COM1)
+ Memory32Fixed (ReadWrite, 0, 0, COM4)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ /* GPIO Community 0 */
+ CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+ Store (^^PCRB (PID_GPIOCOM0), BAS0)
+
+ /* GPIO Community 1 */
+ CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+ Store (^^PCRB (PID_GPIOCOM1), BAS1)
+
+ /* GPIO Community 4 */
+ CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+ Store (^^PCRB (PID_GPIOCOM4), BAS4)
+
+ Return (RBUF)
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0xF)
+ }
+}
+
+/*
+ * Get GPIO DW0 Address
+ * Arg0 - GPIO Number
+ */
+Method (GADD, 1, NotSerialized)
+{
+ /* GPIO Community 0 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_G7)))
+ {
+ Store (PID_GPIOCOM0, Local0)
+ Subtract (Arg0, GPP_A0, Local1)
+ }
+ /* GPIO Community 1 */
+ If (LAnd (LGreaterEqual (Arg0, GPP_D0), LLessEqual (Arg0, GPP_H23)))
+ {
+ Store (PID_GPIOCOM1, Local0)
+ Subtract (Arg0, GPP_D0, Local1)
+ }
+ /* GPIO Community 04*/
+ If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_E23)))
+ {
+ Store (PID_GPIOCOM4, Local0)
+ Subtract (Arg0, GPP_C0, Local1)
+ }
+ Store (PCRB (Local0), Local2)
+ Add (Local2, PAD_CFG_BASE, Local2)
+ Return (Add (Local2, Multiply (Local1, 16)))
+}
+
+/*
+ * Get GPIO Value
+ * Arg0 - GPIO Number
+ */
+Method (GRXS, 1, Serialized)
+{
+ OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
+ Field (PREG, AnyAcc, NoLock, Preserve)
+ {
+ VAL0, 32
+ }
+ And (GPIORXSTATE_MASK, ShiftRight (VAL0, GPIORXSTATE_SHIFT), Local0)
+
+ Return (Local0)
+}
diff --git a/src/soc/intel/cannonlake/acpi/pcr.asl b/src/soc/intel/cannonlake/acpi/pcr.asl
new file mode 100644
index 0000000000..7915226a0a
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/pcr.asl
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/pcr.h>
+
+Method (PCRB, 1, NotSerialized)
+{
+ Return (Add (CONFIG_PCR_BASE_ADDRESS,
+ ShiftLeft (Arg0, PCR_PORTID_SHIFT)))
+}
diff --git a/src/soc/intel/cannonlake/acpi/scs.asl b/src/soc/intel/cannonlake/acpi/scs.asl
new file mode 100644
index 0000000000..11564ae7d4
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/scs.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB.PCI0) {
+
+ /* SD CARD */
+ Device (SDXC)
+ {
+ Name (_ADR, 0x00140005)
+
+ } /* Device (SDXC) */
+}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index 3d6538e200..408c31bfde 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -18,3 +18,12 @@
/* PCI IRQ assignment */
#include "pci_irqs.asl"
+
+/* eMMC, SD Card */
+#include "scs.asl"
+
+/* PCR access */
+#include "pcr.asl"
+
+/* GPIO controller */
+#include "gpio.asl"
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
index 6e84f838f1..9c070171b5 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
@@ -248,4 +248,6 @@
#define GPI_SMI_EN_0 0x1A0
#define PAD_CFG_BASE 0x600
+#define GPIORXSTATE_MASK 0x1
+#define GPIORXSTATE_SHIFT 1
#endif