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authorRichard Spiegel <richard.spiegel@amd.corp-partner.google.com>2018-10-17 13:32:58 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-10-18 12:49:43 +0000
commit6205221a7375f5b54ddee77b303915c593c35599 (patch)
tree4245b83da19cb639a1e3779d390a7d2b855d9fa6 /src
parente7e01116e72205113243e43b0ca1bed4c584c5b3 (diff)
downloadcoreboot-6205221a7375f5b54ddee77b303915c593c35599.tar.xz
soc/amd/stoneyridge: Replace double defined MISC MMIO reg. 0x40
Register 0x40 of miscellaneous MMIO is double defined, with different names, which makes it confusing. Eliminate MISC_MISC_CLK_CNTL_1, and move its only bit definition to MISC_CLK_CNTL1 (which is correctly placed among MMIO registers. BUG=b:117818431 TEST=Build grunt. Change-Id: I5ca5045498b8a81943282e0d6ecfbaecbd600d19 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/29175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h4
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c2
2 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 3d0df6874e..681f14922a 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -132,6 +132,7 @@
#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT)
#define MISC_CLK_CNTL1 0x40
#define CG1PLL_FBDIV_TEST BIT(26)
+#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */
/* XHCI_PM Registers: 0xfed81c00 */
#define XHCI_PM_INDIRECT_INDEX 0x48
@@ -370,9 +371,6 @@
#define SPI100_HOST_PREF_CONFIG 0x2c
#define SPI_RD4DW_EN_HOST BIT(15)
-#define MISC_MISC_CLK_CNTL_1 0x40
-#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */
-
/* Platform Security Processor D8F0 */
#define PSP_MAILBOX_BAR PCI_BASE_ADDRESS_4 /* BKDG: "BAR3" */
#define PSP_BAR_ENABLES 0x48
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 33330a8812..37ebdc115d 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -395,7 +395,7 @@ void sb_clk_output_48Mhz(void)
{
u32 ctrl;
u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE
- + MISC_MISC_CLK_CNTL_1);
+ + MISC_CLK_CNTL1);
/*
* Enable the X14M_25M_48M_OSC pin and leaving it at it's default so