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authorLee Leahy <leroy.p.leahy@intel.com>2017-03-13 17:03:31 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2017-03-14 23:54:37 +0100
commit66b0d55d326540e400ad3fa5130666dbd03b9694 (patch)
tree3e7f3de8c5fab23d581af9db622fd1cef2626c18 /src
parent6edb3140501ad6ad4224e9c79e7d63b8af970466 (diff)
downloadcoreboot-66b0d55d326540e400ad3fa5130666dbd03b9694.tar.xz
soc/intel/quark: Add ESRAM display to FSP 1.1
Add ESRAM display to FSP 1.1 TEST=Build and run on Galileo Gen2 Change-Id: Ia47b0bdba65606a7f0695332d298fc1e910b0e2f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/18804 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/quark/Kconfig1
-rw-r--r--src/soc/intel/quark/romstage/fsp1_1.c33
2 files changed, 33 insertions, 1 deletions
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 8182caa51c..c697b561bd 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -177,7 +177,6 @@ config DCACHE_RAM_SIZE
config DISPLAY_ESRAM_LAYOUT
bool "Display ESRAM layout"
default n
- depends on PLATFORM_USES_FSP2_0
help
Select this option to display coreboot's use of ESRAM.
diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c
index e93e688ea7..84fc5a55ba 100644
--- a/src/soc/intel/quark/romstage/fsp1_1.c
+++ b/src/soc/intel/quark/romstage/fsp1_1.c
@@ -105,6 +105,39 @@ void soc_memory_init_params(struct romstage_params *params,
if (!rmu_file)
die("Microcode file (rmu.bin) not found.");
+ /* Display the ESRAM layout */
+ if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) {
+ printk(BIOS_SPEW, "\nESRAM Layout:\n\n");
+ printk(BIOS_SPEW,
+ "+-------------------+ 0x80080000 - ESRAM end\n");
+ if (_car_relocatable_data_end != (void *)0x80080000) {
+ printk(BIOS_SPEW, "| |\n");
+ printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
+ _car_relocatable_data_end);
+ }
+ printk(BIOS_SPEW, "| coreboot data |\n");
+ printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
+ _car_stack_end);
+ printk(BIOS_SPEW, "| coreboot stack |\n");
+ printk(BIOS_SPEW, "+-------------------+ 0x%p",
+ _car_stack_start);
+ if (IS_ENABLED(CONFIG_SEPARATE_VERSTAGE)) {
+ printk(BIOS_SPEW, "\n");
+ printk(BIOS_SPEW, "| vboot data |\n");
+ printk(BIOS_SPEW, "+-------------------+ 0x%08x",
+ CONFIG_DCACHE_RAM_BASE);
+ }
+ printk(BIOS_SPEW, " (CONFIG_DCACHE_RAM_BASE)\n");
+
+ printk(BIOS_SPEW, "| FSP data |\n");
+ printk(BIOS_SPEW, "+-------------------+\n");
+ printk(BIOS_SPEW, "| FSP stack |\n");
+ printk(BIOS_SPEW, "+-------------------+\n");
+ printk(BIOS_SPEW, "| FSP binary |\n");
+ printk(BIOS_SPEW,
+ "+-------------------+ 0x80000000 - ESRAM start\n\n");
+ }
+
/* Update the UPD data for MemoryInit */
upd->AddrMode = config->AddrMode;
upd->ChanMask = config->ChanMask;