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authorAngel Pons <th3fanbus@gmail.com>2020-07-07 21:47:36 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-10 12:57:22 +0000
commit69c9aa9dc51612d2bd644e8c634e2b6628ea5181 (patch)
tree2f1710e290ba99eece8ed004977c242d742fa1fb /src
parenta13007b49aecaaa04fa1425a08fc98b4eebfb69c (diff)
downloadcoreboot-69c9aa9dc51612d2bd644e8c634e2b6628ea5181.tar.xz
cpu/intel/haswell/finalize.c: Drop dead code
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I3fc616eeb975aae7a5937f8b555ae554010d8dd3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/haswell/finalize.c37
1 files changed, 0 insertions, 37 deletions
diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c
index a6d38ae6f7..1f84b821a9 100644
--- a/src/cpu/intel/haswell/finalize.c
+++ b/src/cpu/intel/haswell/finalize.c
@@ -4,43 +4,6 @@
#include <cpu/x86/msr.h>
#include "haswell.h"
-/* MSR Documentation based on
- * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)"
- * Document Number 504790
- * Revision 1.6.0, June 2012 */
-
void intel_cpu_haswell_finalize_smm(void)
{
-#if 0
- /* Lock C-State MSR */
- msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15);
-
- /* Lock AES-NI only if supported */
- if (cpuid_ecx(1) & (1 << 25))
- msr_set_bit(MSR_FEATURE_CONFIG, 0);
-
-#ifdef LOCK_POWER_CONTROL_REGISTERS
- /*
- * Lock the power control registers.
- *
- * These registers can be left unlocked if modifying power
- * limits from the OS is desirable. Modifying power limits
- * from the OS can be especially useful for experimentation
- * during early phases of system bringup while the thermal
- * power envelope is being proven.
- */
-
- msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31);
- msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31);
- msr_set_bit(MSR_PKG_POWER_LIMIT, 63);
- msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
- msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
-#endif
-
- /* Lock TM interrupts - route thermal events to all processors */
- msr_set_bit(MSR_MISC_PWR_MGMT, 22);
-
- /* Lock memory configuration to protect SMM */
- msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
-#endif
}