diff options
| author | David Hendricks <dhendrix@chromium.org> | 2012-11-05 12:34:09 -0800 |
|---|---|---|
| committer | David Hendricks <dhendrix@chromium.org> | 2012-11-27 02:03:03 +0100 |
| commit | 6b908d08ab4c256b6a8d4f7d863fe9eb65ea6fe3 (patch) | |
| tree | 3890f15a64b2d3ab2917bc3baf633f7489a210d0 /src | |
| parent | d5d340695b84ef6351818236dc514cd9734e87b1 (diff) | |
| download | coreboot-6b908d08ab4c256b6a8d4f7d863fe9eb65ea6fe3.tar.xz | |
Make POST codes written to IO port optional
This adds more configurability to POST codes. The current assumption
is that POST codes should be written to an IO port (e.g. LPC) if POST
codes are enabled. This changes the assumption so that POST codes can
be written to the serial console without being written to an IO port.
This enables POST codes by default using "default y" to avoid
changing current behavior.
Change-Id: I3db91c358ccb1557096983c4d07f70b2e872c4b3
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/1685
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/console/Kconfig | 20 | ||||
| -rw-r--r-- | src/console/post.c | 4 |
2 files changed, 19 insertions, 5 deletions
diff --git a/src/console/Kconfig b/src/console/Kconfig index c1c201227f..303a81d0be 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -360,9 +360,6 @@ config NO_POST bool "Don't show any POST codes" default n -config POST_PORT - hex - default 0x80 config CONSOLE_POST bool "Show POST codes on the debug console" @@ -391,5 +388,20 @@ config CMOS_POST_OFFSET If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value defined in the mainboard option table. -endmenu +config IO_POST + bool "Send POST codes to an IO port" + default y + help + If enabled, POST codes will be written to an IO port. +config IO_POST_PORT + depends on IO_POST + hex "IO port for POST codes" + default 0x80 + help + POST codes on x86 are typically written to the LPC bus on port + 0x80. However, it may be desireable to change the port number + depending on the presence of coprocessors/microcontrollers or if the + platform does not support IO in the conventional x86 manner. + +endmenu diff --git a/src/console/post.c b/src/console/post.c index a565c6bcfb..81a9d398c7 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -100,7 +100,9 @@ void post_code(uint8_t value) #if CONFIG_CMOS_POST cmos_post_code(value); #endif - outb(value, CONFIG_POST_PORT); +#if CONFIG_IO_POST + outb(value, CONFIG_IO_POST_PORT); +#endif #endif mainboard_post(value); } |