diff options
| author | Nico Huber <nico.h@gmx.de> | 2018-05-27 14:37:52 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-04 08:22:20 +0000 |
| commit | 6ea6775fa3eaa78b5322833940b9ba32d784556b (patch) | |
| tree | fed449179d0025ee3efcc697f1755b676fac3baa /src | |
| parent | 089b9089c111da9175d87c4f2671ba8ebe353b4b (diff) | |
| download | coreboot-6ea6775fa3eaa78b5322833940b9ba32d784556b.tar.xz | |
soc/{amd,intel}: Use postcar_frame_add_romcache()
Change-Id: Iee816628ac3c33633f5f45798562a4ce49493a65
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/romstage.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/romstage.c | 5 | ||||
| -rw-r--r-- | src/soc/intel/quark/romstage/fsp2_0.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage_fsp20.c | 3 |
6 files changed, 7 insertions, 14 deletions
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index c8efe30fc1..a742cd062d 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -128,8 +128,7 @@ asmlinkage void car_stage_entry(void) MTRR_TYPE_WRBACK); /* Cache the memory-mapped boot media. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); /* * Cache the TSEG region at the top of ram. This region is diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 5996124207..d2353f1743 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -233,9 +233,7 @@ asmlinkage void car_stage_entry(void) MTRR_TYPE_WRBACK); /* Cache the memory-mapped boot media. */ - if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); /* * Cache the TSEG region at the top of ram. This region is diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index b6cfdbaa8e..ae1ba4d7d0 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -142,8 +142,7 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); run_postcar_phase(&pcf); } diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 7073627a79..105298e8b0 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -172,9 +172,8 @@ asmlinkage void car_stage_entry(void) MTRR_TYPE_WRBACK); /* Cache the memory-mapped boot media. */ - if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) /* * Cache the TSEG region at the top of ram. This region is diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 74796448c4..900ec1b4ca 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -80,8 +80,7 @@ asmlinkage void *car_stage_c_entry(void) postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); /* Cache SPI flash - Write protect not supported */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRTHROUGH); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRTHROUGH); run_postcar_phase(&pcf); return NULL; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index a93407620b..64f9d7d2be 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -186,8 +186,7 @@ asmlinkage void car_stage_entry(void) } /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); + postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); run_postcar_phase(&pcf); } |