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authorElyes HAOUAS <ehaouas@noos.fr>2018-12-05 10:56:30 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-12-20 22:16:24 +0000
commit6f01f4307c993c60813ea332174ca23c2bc269e8 (patch)
tree83d1710b9f70357426e7d2a03b7381e673750e61 /src
parent096833fef4eb5616a95559bb2931dc5e8c0cf594 (diff)
downloadcoreboot-6f01f4307c993c60813ea332174ca23c2bc269e8.tar.xz
soc/intel: Get rid of device_t
Use of device_t is deprecated. Change-Id: Ic29891d78514db3b7eed48414a14e4ff579436c0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30004 Reviewed-by: David Guckian Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/memmap.c8
-rw-r--r--src/soc/intel/common/block/pcr/pcr.c6
-rw-r--r--src/soc/intel/denverton_ns/include/soc/soc_util.h15
-rw-r--r--src/soc/intel/denverton_ns/soc_util.c90
-rw-r--r--src/soc/intel/quark/include/soc/reg_access.h2
-rw-r--r--src/soc/intel/quark/include/soc/storage_test.h15
-rw-r--r--src/soc/intel/quark/romstage/fsp2_0.c2
-rw-r--r--src/soc/intel/quark/storage_test.c14
-rw-r--r--src/soc/intel/skylake/elog.c31
9 files changed, 134 insertions, 49 deletions
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index 6d68501162..be15e165ec 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -15,14 +15,6 @@
* GNU General Public License for more details.
*/
-/*
- * The device_t returned by dev_find_slot() is different than the device_t
- * passed to pci_write_config32(). If one needs to get access to the config.h
- * of a device and perform i/o things are incorrect. One is a pointer while
- * the other is a 32-bit integer.
- */
-#define __SIMPLE_DEVICE__
-
#include <arch/io.h>
#include <assert.h>
#include <cbmem.h>
diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c
index 58eb13affa..804ccff39b 100644
--- a/src/soc/intel/common/block/pcr/pcr.c
+++ b/src/soc/intel/common/block/pcr/pcr.c
@@ -221,7 +221,11 @@ void pcr_or8(uint8_t pid, uint16_t offset, uint8_t ordata)
#if !IS_ENABLED(CONFIG_PCR_COMMON_IOSF_1_0)
-static int pcr_wait_for_completion(device_t dev)
+#ifdef __SIMPLE_DEVICE__
+static int pcr_wait_for_completion(pci_devfn_t dev)
+#else
+static int pcr_wait_for_completion(struct device *dev)
+#endif
{
struct stopwatch sw;
diff --git a/src/soc/intel/denverton_ns/include/soc/soc_util.h b/src/soc/intel/denverton_ns/include/soc/soc_util.h
index 074ec16933..91bd12eead 100644
--- a/src/soc/intel/denverton_ns/include/soc/soc_util.h
+++ b/src/soc/intel/denverton_ns/include/soc/soc_util.h
@@ -28,10 +28,17 @@ typedef enum {
} silicon_revision;
/* soc_util.c */
-device_t get_hostbridge_dev(void);
-device_t get_lpc_dev(void);
-device_t get_pmc_dev(void);
-device_t get_smbus_dev(void);
+#ifdef __SIMPLE_DEVICE__
+pci_devfn_t get_hostbridge_dev(void);
+pci_devfn_t get_lpc_dev(void);
+pci_devfn_t get_pmc_dev(void);
+pci_devfn_t get_smbus_dev(void);
+#else
+struct device *get_hostbridge_dev(void);
+struct device *get_lpc_dev(void);
+struct device *get_pmc_dev(void);
+struct device *get_smbus_dev(void);
+#endif
uint32_t get_pciebase(void);
uint32_t get_pcielength(void);
diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c
index 780695a573..b56c8396d9 100644
--- a/src/soc/intel/denverton_ns/soc_util.c
+++ b/src/soc/intel/denverton_ns/soc_util.c
@@ -28,45 +28,61 @@
#include <soc/pci_devs.h>
#include <soc/systemagent.h>
-device_t get_hostbridge_dev(void)
+#ifdef __SIMPLE_DEVICE__
+pci_devfn_t get_hostbridge_dev(void)
{
-#if defined(__PRE_RAM__) || defined(__SMM__)
return PCI_DEV(0, SA_DEV, SA_FUNC);
+}
#else
+struct device *get_hostbridge_dev(void)
+{
return dev_find_slot(0, PCI_DEVFN(SA_DEV, SA_FUNC));
-#endif
}
+#endif
-device_t get_lpc_dev(void)
+#ifdef __SIMPLE_DEVICE__
+pci_devfn_t get_lpc_dev(void)
{
-#if defined(__PRE_RAM__) || defined(__SMM__)
return PCI_DEV(0, LPC_DEV, LPC_FUNC);
+}
#else
+struct device *get_lpc_dev(void)
+{
return dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
-#endif
}
+#endif
-device_t get_pmc_dev(void)
+#ifdef __SIMPLE_DEVICE__
+pci_devfn_t get_pmc_dev(void)
{
-#if defined(__PRE_RAM__) || defined(__SMM__)
return PCI_DEV(0, PMC_DEV, PMC_FUNC);
+}
#else
+struct device *get_pmc_dev(void)
+{
return dev_find_slot(0, PCI_DEVFN(PMC_DEV, PMC_FUNC));
-#endif
}
+#endif
-device_t get_smbus_dev(void)
+#ifdef __SIMPLE_DEVICE__
+pci_devfn_t get_smbus_dev(void)
{
-#if defined(__PRE_RAM__) || defined(__SMM__)
return PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC);
+}
#else
+struct device *get_smbus_dev(void)
+{
return dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC));
-#endif
}
+#endif
uint32_t get_pciebase(void)
{
- device_t dev;
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
u32 pciexbar_reg;
dev = get_hostbridge_dev();
@@ -98,7 +114,11 @@ uint32_t get_pciebase(void)
uint32_t get_pcielength(void)
{
- device_t dev;
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
u32 pciexbar_reg;
dev = get_hostbridge_dev();
@@ -130,7 +150,12 @@ uint32_t get_pcielength(void)
uint32_t get_tseg_memory(void)
{
- device_t dev = get_hostbridge_dev();
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
+ dev = get_hostbridge_dev();
if (!dev)
return 0;
@@ -140,7 +165,12 @@ uint32_t get_tseg_memory(void)
uint32_t get_top_of_low_memory(void)
{
- device_t dev = get_hostbridge_dev();
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
+ dev = get_hostbridge_dev();
if (!dev)
return 0;
@@ -150,7 +180,12 @@ uint32_t get_top_of_low_memory(void)
uint64_t get_top_of_upper_memory(void)
{
- device_t dev = get_hostbridge_dev();
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
+ dev = get_hostbridge_dev();
if (!dev)
return 0;
@@ -162,7 +197,12 @@ uint64_t get_top_of_upper_memory(void)
uint16_t get_pmbase(void)
{
- device_t dev = get_pmc_dev();
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
+ dev = get_pmc_dev();
if (!dev)
return 0;
@@ -172,7 +212,12 @@ uint16_t get_pmbase(void)
uint16_t get_tcobase(void)
{
- device_t dev = get_smbus_dev();
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
+ dev = get_smbus_dev();
if (!dev)
return 0;
@@ -193,7 +238,12 @@ void mmio_andthenor32(void *addr, uint32_t val2and, uint32_t val2or)
uint8_t silicon_stepping(void)
{
uint8_t revision_id;
- device_t dev = get_lpc_dev();
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
+ dev = get_lpc_dev();
if (!dev)
return 0;
diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h
index 1695297898..ba340a0ca5 100644
--- a/src/soc/intel/quark/include/soc/reg_access.h
+++ b/src/soc/intel/quark/include/soc/reg_access.h
@@ -16,8 +16,6 @@
#ifndef _QUARK_REG_ACCESS_H_
#define _QUARK_REG_ACCESS_H_
-#define __SIMPLE_DEVICE__
-
#include <arch/io.h>
#include <cpu/x86/cr.h>
#include <cpu/x86/msr.h>
diff --git a/src/soc/intel/quark/include/soc/storage_test.h b/src/soc/intel/quark/include/soc/storage_test.h
index cae296fe59..62c9e79236 100644
--- a/src/soc/intel/quark/include/soc/storage_test.h
+++ b/src/soc/intel/quark/include/soc/storage_test.h
@@ -22,16 +22,19 @@
#include <timer.h>
#ifdef __SIMPLE_DEVICE__
-#define dev_t uintptr_t
+uint32_t storage_test_init(pci_devfn_t dev, uint32_t *previous_bar,
+ uint16_t *previous_command);
+void storage_test(uint32_t bar, int full_initialization);
+void storage_test_complete(pci_devfn_t dev, uint32_t previous_bar,
+ uint16_t previous_command);
#else
-#define dev_t device_t
-#endif /* __SIMPLE_DEVICE__ */
-
-uint32_t storage_test_init(dev_t dev, uint32_t *previous_bar,
+uint32_t storage_test_init(struct device *dev, uint32_t *previous_bar,
uint16_t *previous_command);
void storage_test(uint32_t bar, int full_initialization);
-void storage_test_complete(dev_t dev, uint32_t previous_bar,
+void storage_test_complete(struct device *dev, uint32_t previous_bar,
uint16_t previous_command);
+#endif
+
/* Logging support */
struct log_entry {
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index 900ec1b4ca..3e6198805d 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -38,7 +38,7 @@ asmlinkage void *car_stage_c_entry(void)
if (IS_ENABLED(CONFIG_STORAGE_TEST)) {
uint32_t bar;
- dev_t dev;
+ pci_devfn_t dev;
uint32_t previous_bar;
uint16_t previous_command;
diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c
index 507fa9260c..0a5e22d9c2 100644
--- a/src/soc/intel/quark/storage_test.c
+++ b/src/soc/intel/quark/storage_test.c
@@ -39,8 +39,13 @@ extern uint8_t _car_drivers_storage_end;
#define STORAGE_DEBUG BIOS_DEBUG
#define LOG_DEBUG (IS_ENABLED(CONFIG_STORAGE_LOG) ? STORAGE_DEBUG : BIOS_NEVER)
-uint32_t storage_test_init(dev_t dev, uint32_t *previous_bar,
+#ifdef __SIMPLE_DEVICE__
+uint32_t storage_test_init(pci_devfn_t dev, uint32_t *previous_bar,
uint16_t *previous_command)
+#else
+uint32_t storage_test_init(struct device *dev, uint32_t *previous_bar,
+ uint16_t *previous_command)
+#endif
{
uint32_t bar;
@@ -67,8 +72,13 @@ uint32_t storage_test_init(dev_t dev, uint32_t *previous_bar,
return bar;
}
-void storage_test_complete(dev_t dev, uint32_t previous_bar,
+#ifdef __SIMPLE_DEVICE__
+void storage_test_complete(pci_devfn_t dev, uint32_t previous_bar,
uint16_t previous_command)
+#else
+void storage_test_complete(struct device *dev, uint32_t previous_bar,
+ uint16_t previous_command)
+#endif
{
pci_write_config16(dev, PCI_COMMAND, previous_command);
pci_write_config32(dev, PCI_BASE_ADDRESS_0, previous_bar);
diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c
index a2fa52ac1f..1fab92e2b0 100644
--- a/src/soc/intel/skylake/elog.c
+++ b/src/soc/intel/skylake/elog.c
@@ -159,7 +159,11 @@ static inline bool pch_xhci_usb3_update_wake_event(uintptr_t mmio_base)
ELOG_WAKE_SOURCE_PME_XHCI_USB_3);
}
-static bool pch_xhci_update_wake_event(device_t dev)
+#ifdef __SIMPLE_DEVICE__
+static bool pch_xhci_update_wake_event(pci_devfn_t dev)
+#else
+static bool pch_xhci_update_wake_event(struct device *dev)
+#endif
{
uintptr_t mmio_base;
bool event_found = false;
@@ -175,15 +179,24 @@ static bool pch_xhci_update_wake_event(device_t dev)
}
struct pme_status_info {
- device_t dev;
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
uint8_t reg_offset;
uint32_t elog_event;
};
#define PME_STS_BIT (1 << 15)
+#ifdef __SIMPLE_DEVICE__
static void pch_log_add_elog_event(const struct pme_status_info *info,
- device_t dev)
+ pci_devfn_t dev)
+#else
+static void pch_log_add_elog_event(const struct pme_status_info *info,
+ struct device *dev)
+#endif
{
/*
* If wake source is XHCI, check for detailed wake source events on
@@ -198,7 +211,11 @@ static void pch_log_add_elog_event(const struct pme_status_info *info,
static void pch_log_pme_internal_wake_source(void)
{
size_t i;
- device_t dev;
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
uint16_t val;
bool dev_found = false;
@@ -243,7 +260,11 @@ static void pch_log_pme_internal_wake_source(void)
static void pch_log_rp_wake_source(void)
{
size_t i;
- device_t dev;
+#ifdef __SIMPLE_DEVICE__
+ pci_devfn_t dev;
+#else
+ struct device *dev;
+#endif
uint32_t val;
struct pme_status_info pme_status_info[] = {