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authorJeremy Soller <jeremy@system76.com>2020-07-21 09:22:50 -0600
committerMichael Niewöhner <foss@mniewoehner.de>2020-09-17 20:47:49 +0000
commit748bfac734b0cabfa0e2684886e434ece4a077f1 (patch)
treea269fbc9a7d30fd651cff5f289d810aa0f7de97d /src
parent75594e9ff7b6dca1c295dc4be66343e78464c8a0 (diff)
downloadcoreboot-748bfac734b0cabfa0e2684886e434ece4a077f1.tar.xz
mb/system76/lemp9: skip FSP init of UART2
This UART is already initialized by coreboot for the console, it does not need to be initialized by the FSP. Tested on lemp9. Signed-off-by: Jeremy Soller <jeremy@system76.com> Change-Id: I7c299fd7cf6fe53d1f500a899a14e63e51ad6266 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/system76/lemp9/devicetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb
index 15790809b5..f8b3009994 100644
--- a/src/mainboard/system76/lemp9/devicetree.cb
+++ b/src/mainboard/system76/lemp9/devicetree.cb
@@ -43,6 +43,7 @@ chip soc/intel/cannonlake
# Serial I/O
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad
+ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // LPSS UART
}"
# Misc