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authorAamir Bohra <aamir.bohra@intel.com>2020-05-28 10:00:16 +0530
committerKarthik Ramasubramanian <kramasub@google.com>2020-05-29 23:19:35 +0000
commit74b1919f1779a3a3b1a0320482784bb31234b175 (patch)
treea3d64b34c0caadb5b09299a577cb182192d11438 /src
parent11217de375598c7a6f6288d0bc04dec115e41df5 (diff)
downloadcoreboot-74b1919f1779a3a3b1a0320482784bb31234b175.tar.xz
mb/google/dedede: Enable Heci1 device
Enable heci1 device from devicetree for PCI enumeration. This is required for ME status dump using HFSTSx resgisters in PCI config space. Heci1 device is later disabled through heci disable flow. TEST=Build, boot waddledoo. ME status dump is seen in console logs. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: Icb77db3f0666c2d14ebef2c3214564346d1fd3c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/dedede/variants/baseboard/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
index 1b42dfb81a..fc4397689e 100644
--- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -258,7 +258,7 @@ chip soc/intel/jasperlake
device pci 15.1 on end # I2C 1
device pci 15.2 on end # I2C 2
device pci 15.3 on end # I2C 3
- device pci 16.0 off end # HECI 1
+ device pci 16.0 on end # HECI 1
device pci 16.1 off end # HECI 2
device pci 16.4 off end # HECI 3
device pci 16.5 off end # HECI 4