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authorDaniel Kurtz <djkurtz@chromium.org>2019-01-17 12:32:10 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-01-23 14:56:43 +0000
commit75ebb6c5dfa25d0f642faf5b253290dfacc59033 (patch)
treea2ecf0b4412ee59f341c77c7e9841b9bfe2f6eca /src
parent01f96d78ffdcf5b60079c5804ca99076cbda5d95 (diff)
downloadcoreboot-75ebb6c5dfa25d0f642faf5b253290dfacc59033.tar.xz
soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeout
It is possible to configure debounce, but leave it disabled by specifying a 0 value for the timeout. Add a define for allowing to do so via the PAD_DEBOUNCE() macro. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> BUG=b:113880780 BRANCH=none TEST=compile Change-Id: I9de61297b0677cc904535a51c16970eecb52021d Reviewed-on: https://review.coreboot.org/c/30998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/gpio.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index 04eda4934e..47eae84c86 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -462,6 +462,7 @@ enum {
#define GPIO_TIMEBASE_15560uS (1 << 7)
#define GPIO_TIMEBASE_62440uS (GPIO_TIMEBASE_183uS | \
GPIO_TIMEBASE_15560uS)
+#define GPIO_IN_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS)
#define GPIO_IN_60uS (1 | GPIO_TIMEBASE_61uS)
#define GPIO_IN_120uS (2 | GPIO_TIMEBASE_61uS)
#define GPIO_IN_200uS (3 | GPIO_TIMEBASE_61uS)