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authorLijian Zhao <lijian.zhao@intel.com>2019-04-22 21:17:58 +0000
committerDuncan Laurie <dlaurie@chromium.org>2019-04-22 21:35:45 +0000
commit7f1a0e6b4c6a319d3cd552c708195d94b99bbb97 (patch)
tree799d6ed0f6794555f094f1d7d8dec6a059fe027a /src
parent69eae2762fc34f8303e8a41065df437295262586 (diff)
downloadcoreboot-7f1a0e6b4c6a319d3cd552c708195d94b99bbb97.tar.xz
Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"
This reverts commit 41dad286d846819242a84fc65faed2bbb35845ac. The change will make s0ix fail on Sarien/Arcada Platform. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I169bc6f41fba82fcf515267e8e1d08aa5ee2dce4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32391 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/cannonlake/Kconfig8
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c5
-rw-r--r--src/soc/intel/cannonlake/romstage/fsp_params.c5
3 files changed, 1 insertions, 17 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 026aaf20ff..40b40d65ad 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -27,8 +27,6 @@ config SOC_INTEL_WHISKEYLAKE
bool
default n
select SOC_INTEL_COMMON_CANNONLAKE_BASE
- select FSP_PEIM_TO_PEIM_INTERFACE
- select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
help
Intel Whiskeylake support
@@ -36,12 +34,6 @@ config SOC_INTEL_COMETLAKE
bool
default n
select SOC_INTEL_COMMON_CANNONLAKE_BASE
- # TODO:
- # Delete FSP_PEIM_TO_PEIM_INTERFACE and
- # USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI selection
- # and select PLATFORM_USES_FSP2_1 once FSP support for CML is ready
- select FSP_PEIM_TO_PEIM_INTERFACE
- select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
help
Intel Cometlake support
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 1fd42cda17..b8dba184cb 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -18,9 +18,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <fsp/api.h>
-#include <fsp/ppi/mp_service_ppi.h>
#include <fsp/util.h>
-#include <intelblocks/mp_init.h>
#include <intelblocks/xdci.h>
#include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h>
@@ -144,9 +142,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Usb3OverCurrentPin[i] = 0;
}
- if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
- params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
-
mainboard_silicon_init_params(params);
/* Set PsysPmax if it is available from DT */
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 2ad2c935b7..86160f68ae 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -65,10 +65,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)
- if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
- m_cfg->SkipMpInit = 0;
- else
- m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
+ m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
#endif
/* Set CpuRatio to match existing MSR value */