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authorBora Guvendik <bora.guvendik@intel.com>2018-06-13 14:46:10 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-06-21 15:55:05 +0000
commit7fe9e8edea0dd07d0980d85b3f43c96ca486ab0a (patch)
tree13c589ba86429f2a9ab1f23141eb31b89b7570ff /src
parent90d3b2b0c0d63d58d75cf28616724a41e7951e58 (diff)
downloadcoreboot-7fe9e8edea0dd07d0980d85b3f43c96ca486ab0a.tar.xz
soc/intel/apollolake: unify definition for spi base address
Use SPI_BASE_ADDRESS instead of PRERAM_SPI_BASE_ADDRESS like big core in order make common code implementation straightforward. Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/27097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/bootblock/bootblock.c2
-rw-r--r--src/soc/intel/apollolake/include/soc/iomap.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index c7ababd216..ead6bf3f03 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -106,7 +106,7 @@ void bootblock_soc_early_init(void)
enable_pm_timer_emulation();
- fast_spi_early_init(PRERAM_SPI_BASE_ADDRESS);
+ fast_spi_early_init(SPI_BASE_ADDRESS);
fast_spi_cache_bios_region();
diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h
index 9a2500cd45..479882f47c 100644
--- a/src/soc/intel/apollolake/include/soc/iomap.h
+++ b/src/soc/intel/apollolake/include/soc/iomap.h
@@ -47,7 +47,7 @@
#define HECI1_BASE_ADDRESS 0xfed1a000
/* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */
-#define PRERAM_SPI_BASE_ADDRESS 0xfe010000
+#define SPI_BASE_ADDRESS 0xfe010000
#define EARLY_GSPI_BASE_ADDRESS 0xfe011000
/* Temporary BAR for early I2C bus access */