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authorNico Huber <nico.huber@secunet.com>2015-10-21 15:43:41 +0200
committerNico Huber <nico.h@gmx.de>2015-10-22 23:04:55 +0200
commit8193b068d49478e036c0d2ed3e3f717d767eedde (patch)
tree198849908b318c0ad17c49936238493f6afb8af6 /src
parent37743a913fd77fd7ef6b4bb24fadecaea7b52429 (diff)
downloadcoreboot-8193b068d49478e036c0d2ed3e3f717d767eedde.tar.xz
allocator: Page align memory mapped PCI resources
To help hypervisors to assign PCI devices individually to virtualization guests, page align dynamically allocated MMIO resources. Tested with kontron/ktqm77 which has dynamically configured onboard devices on the root bus and secondary buses. Booted Linux and checked the configuration with `lspci -v`. Got the configuration through Muen's tools which are very picky about overlapping and alignment. Booted a Muen based system that uses many onboard devices. GMA, xHCI and one NIC (on a secondary bus) were verified to function properly. Change-Id: I2b7115070e1ccad64565feff025289732c3b5e66 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/12111 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/device/pci_device.c6
-rw-r--r--src/include/device/pci_def.h7
2 files changed, 13 insertions, 0 deletions
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index f2e4d5d2c1..cf2f74f81a 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -211,6 +211,12 @@ struct resource *pci_get_resource(struct device *dev, unsigned long index)
resource->gran += 1;
}
resource->limit = limit = moving | (resource->size - 1);
+
+ if (pci_base_address_is_memory_space(attr)) {
+ /* Page-align to allow individual mapping of devices. */
+ if (resource->align < 12)
+ resource->align = 12;
+ }
}
/*
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index ef3427b4e7..04cf945527 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -78,6 +78,13 @@
#define PCI_BASE_ADDRESS_IO_ATTR_MASK 0x03
/* bit 1 is reserved if address_space = 1 */
+#ifndef __ROMCC__
+static inline int pci_base_address_is_memory_space(unsigned int attr)
+{
+ return (attr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY;
+}
+#endif
+
/* Header type 0 (normal devices) */
#define PCI_CARDBUS_CIS 0x28
#define PCI_SUBSYSTEM_VENDOR_ID 0x2c