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authorJimmy Zhang <jimmzhang@nvidia.com>2014-04-07 15:45:08 -0700
committerMarc Jones <marc.jones@se-eng.com>2014-12-15 20:15:36 +0100
commit846f34422637aded923537e29b1a5e2ad634a97d (patch)
tree3764df2f666944cb63c763079f6c4f2d1e9c2d80 /src
parent46e097598732ee2993091be0c46f42d2b1802424 (diff)
downloadcoreboot-846f34422637aded923537e29b1a5e2ad634a97d.tar.xz
tegra124: set safe values for href_to_sync and vref_to_sync
href_to_sync and vref_to_sync are chip specific settings. Currently they are set to 1/2 of hfront_porch and vfront_porch respectively. However, to support EDID (CL192730), per David Ung, the safe values for both are 1 (the same settings as in kernel). BUG=none BRANCH=none TEST=built and booted on nyan. Original-Change-Id: Ifb8898e720a160ba044e2b526de2a4d17bc63672 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/193504 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org> Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org> Original-Tested-by: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit a7128a533ba6083ddfeeca3ba0828962cc2c8ab6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I6954a5b49c798ebdffb20e3ebc9099cd17591b79 Reviewed-on: http://review.coreboot.org/7758 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/nyan/devicetree.cb4
-rw-r--r--src/mainboard/google/nyan_big/devicetree.cb4
-rw-r--r--src/mainboard/google/nyan_blaze/devicetree.cb4
3 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb
index bf6c7f3bb3..600bdbef7b 100644
--- a/src/mainboard/google/nyan/devicetree.cb
+++ b/src/mainboard/google/nyan/devicetree.cb
@@ -69,12 +69,12 @@ chip soc/nvidia/tegra124
# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
# h: width 1366 start 1502 end 1532 total 1592
# v: height 768 start 776 end 788 total 800
- register "href_to_sync" = "68"
+ register "href_to_sync" = "1"
register "hfront_porch" = "136"
register "hsync_width" = "30"
register "hback_porch" = "60"
- register "vref_to_sync" = "4"
+ register "vref_to_sync" = "1"
register "vfront_porch" = "8"
register "vsync_width" = "12"
register "vback_porch" = "12"
diff --git a/src/mainboard/google/nyan_big/devicetree.cb b/src/mainboard/google/nyan_big/devicetree.cb
index bf6c7f3bb3..600bdbef7b 100644
--- a/src/mainboard/google/nyan_big/devicetree.cb
+++ b/src/mainboard/google/nyan_big/devicetree.cb
@@ -69,12 +69,12 @@ chip soc/nvidia/tegra124
# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
# h: width 1366 start 1502 end 1532 total 1592
# v: height 768 start 776 end 788 total 800
- register "href_to_sync" = "68"
+ register "href_to_sync" = "1"
register "hfront_porch" = "136"
register "hsync_width" = "30"
register "hback_porch" = "60"
- register "vref_to_sync" = "4"
+ register "vref_to_sync" = "1"
register "vfront_porch" = "8"
register "vsync_width" = "12"
register "vback_porch" = "12"
diff --git a/src/mainboard/google/nyan_blaze/devicetree.cb b/src/mainboard/google/nyan_blaze/devicetree.cb
index bf6c7f3bb3..600bdbef7b 100644
--- a/src/mainboard/google/nyan_blaze/devicetree.cb
+++ b/src/mainboard/google/nyan_blaze/devicetree.cb
@@ -69,12 +69,12 @@ chip soc/nvidia/tegra124
# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
# h: width 1366 start 1502 end 1532 total 1592
# v: height 768 start 776 end 788 total 800
- register "href_to_sync" = "68"
+ register "href_to_sync" = "1"
register "hfront_porch" = "136"
register "hsync_width" = "30"
register "hback_porch" = "60"
- register "vref_to_sync" = "4"
+ register "vref_to_sync" = "1"
register "vfront_porch" = "8"
register "vsync_width" = "12"
register "vback_porch" = "12"