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authorKrishna Prasad Bhat <krishna.p.bhat.d@intel.com>2019-03-30 10:42:23 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-04-01 07:53:05 +0000
commit847289d49e8b0ab375f1d8dc9eaf6ecf707aa21f (patch)
tree7304c392921a6bd44f0ee1286f5ff6b604e5e037 /src
parentdffa8d05e3694df9cce1ad1b201ea02528038695 (diff)
downloadcoreboot-847289d49e8b0ab375f1d8dc9eaf6ecf707aa21f.tar.xz
mb/google/hatch: Unlock GPIO pads
GPP_A12 is being used as FPMCU_RST in hatch. This GPIO is being padlocked in FSP and cannot used in kernel. Hence unlock the GPIO pads to export this pin in kernel to be used as FPMCU_RST. BUG=b:128686027 BRANCH=None TEST=Read Pad Configuration Lock (PADCFGLOCK_GPP_A_0) register. localhost /sys/class/gpio # iotools mmio_read32 0xfd6e0080 0x00000000 localhost /sys/class/gpio # echo 212 > export Change-Id: Ie0439956e6c8e386435e535665ccaf2ab82adeb0 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32126 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/devicetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index dc7cc24916..984852f6cf 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -73,6 +73,8 @@ chip soc/intel/cannonlake
register "DdiPortBHpd" = "1"
register "DdiPortCHpd" = "1"
register "tcc_offset" = "10" # TCC of 90C
+ # Unlock GPIO pads
+ register "PchUnlockGpioPads" = "1"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1