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| author | Duncan Laurie <dlaurie@chromium.org> | 2014-07-31 10:46:57 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-03-27 05:38:37 +0100 |
| commit | 84b9cf4756ff5cda10d4683c5957b6748c3ca377 (patch) | |
| tree | 77d3ed3211142c2bb56b28087c53a330ca7dcd0f /src | |
| parent | 7b24df41608830bb6368179685e4d92f13a2f505 (diff) | |
| download | coreboot-84b9cf4756ff5cda10d4683c5957b6748c3ca377.tar.xz | |
broadwell: Tweak GFXPAUSE settings based on revision
Changes from 2.1.0 reference code release.
BUG=chrome-os-partner:28234
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: I6110a9bdb2973f1a134d8105c37659bf43f61d34
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/210607
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ef660ddc6c17a003f06b8995e821c7642c49a56e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibb41cd7369cfc7b9b86b61460650a56415b3d8fb
Reviewed-on: http://review.coreboot.org/8949
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/broadwell/broadwell/systemagent.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/igd.c | 14 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/systemagent.c | 5 |
3 files changed, 20 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/broadwell/systemagent.h b/src/soc/intel/broadwell/broadwell/systemagent.h index f95370b2b5..c3b5f942e6 100644 --- a/src/soc/intel/broadwell/broadwell/systemagent.h +++ b/src/soc/intel/broadwell/broadwell/systemagent.h @@ -122,4 +122,7 @@ /* Data is passed through bits 31:0 of the data register. */ #define BIOS_MAILBOX_DATA 0x5da0 +/* System Agent identification */ +u8 systemagent_revision(void); + #endif diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 31293e5ed3..53d108def5 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -148,8 +148,7 @@ static const struct reg_script broadwell_early_init_script[] = { REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa250, 0x000000ff), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa25c, 0x00000010), - /* GFXPAUSE settings */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00030020), + /* GFXPAUSE settings (set based on stepping) */ /* ECO Settings */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x45200000), @@ -167,6 +166,9 @@ static const struct reg_script broadwell_early_init_script[] = { /* Video Frequency Request */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa00c, 0x08000000), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x138158, 0x00000009), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x13815c, 0x0000000d), + /* * RC6 Settings */ @@ -489,6 +491,14 @@ static void igd_init(struct device *dev) /* Early init steps */ if (is_broadwell) { reg_script_run_on_dev(dev, broadwell_early_init_script); + + /* Set GFXPAUSE based on stepping */ + if (cpu_stepping() <= (CPUID_BROADWELL_E0 & 0xf) && + systemagent_revision() <= 9) { + gtt_write(0xa000, 0x300ff); + } else { + gtt_write(0xa000, 0x30020); + } } else { reg_script_run_on_dev(dev, haswell_early_init_script); } diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index ac021fb9ef..0488ccbe4c 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -36,6 +36,11 @@ #include <broadwell/ramstage.h> #include <broadwell/systemagent.h> +u8 systemagent_revision(void) +{ + return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); +} + static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; |