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authorMartin Roth <martinroth@chromium.org>2020-02-05 16:46:30 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-06-14 19:08:08 +0000
commit86ba0d73f34185533e5e2d4258aa3bf3dba40ed4 (patch)
tree5b2f8f95c783997eee1f1aad0049559a71ebc7cb /src
parent33d9c4ad7e9e8048e90858edd8e0212e23a0ac8e (diff)
downloadcoreboot-86ba0d73f34185533e5e2d4258aa3bf3dba40ed4.tar.xz
soc/amd/picasso/graphics: implement map_oprom_vendev_rev
Picasso, Dali, and Pollock iGPU share the same PCI device ID, but need different video BIOSes. This checks the vendor & device IDs along with the revision and selects the correct video BIOS to use. Also add the second VGA BIOS for Raven2-based SoCs and change all VGA BIOS IDs to the format including the revision number. Since SeaBIOS still expects the CBFS file name without the revision ID, it won't find the VBIOS any more. As a temporary workaround add the VBIOS for the silicon it will run on as VGA_BIOS_DGPU_*. Change-Id: I8f48ecc3fbffddd21d1f830fbee26a09ac351e1c Signed-off-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://chromium-review.googlesource.com/2040455 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/picasso/Kconfig30
-rw-r--r--src/soc/amd/picasso/Makefile.inc1
-rw-r--r--src/soc/amd/picasso/graphics.c22
-rw-r--r--src/soc/amd/picasso/include/soc/cpu.h5
4 files changed, 56 insertions, 2 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 27901ba600..e23cfd8f87 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -194,15 +194,41 @@ config VERSTAGE_ADDR
config VGA_BIOS_ID
string
- default "1002,15d8"
+ default "1002,15d8,c1"
help
The default VGA BIOS PCI vendor/device ID should be set to the
- result of the map_oprom_vendev() function in northbridge.c.
+ result of the map_oprom_vendev_rev() function in northbridge.c.
config VGA_BIOS_FILE
string
default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin"
+config VGA_BIOS_SECOND
+ def_bool y
+
+config VGA_BIOS_SECOND_ID
+ string
+ default "1002,15dd,c4"
+ help
+ Because Dali and Picasso need different video BIOSes, but have the
+ same vendor/device IDs, we need an alternate method to determine the
+ correct video BIOS. In map_oprom_vendev_rev(), we look at the cpuid
+ and decide which rom to load.
+
+ Even though the hardware has the same vendor/device IDs, the vBIOS
+ contains a *different* device ID, confusing the situation even more.
+
+config VGA_BIOS_SECOND_FILE
+ string
+ default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin"
+
+config CHECK_REV_IN_OPROM_NAME
+ bool
+ default y
+ help
+ Select this in the platform BIOS or chipset if the option rom has a
+ revision that needs to be checked when searching CBFS.
+
config S3_VGA_ROM_RUN
bool
default n
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 7b80b21c78..03ce272d4d 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -69,6 +69,7 @@ ramstage-y += psp.c
ramstage-y += fsp_params.c
ramstage-y += config.c
ramstage-y += update_microcode.c
+ramstage-y += graphics.c
all-y += reset.c
diff --git a/src/soc/amd/picasso/graphics.c b/src/soc/amd/picasso/graphics.c
new file mode 100644
index 0000000000..047559cbf3
--- /dev/null
+++ b/src/soc/amd/picasso/graphics.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/pci_rom.h>
+#include <soc/cpu.h>
+#include <soc/soc_util.h>
+
+void map_oprom_vendev_rev(u32 *vendev, u8 *rev)
+{
+ if (*vendev != PICASSO_VBIOS_VID_DID)
+ return;
+
+ /* Check if the RV2 video bios needs to be used instead of the RV1/PCO one */
+ if (soc_is_raven2()) {
+ printk(BIOS_NOTICE, "Using RV2 VBIOS.\n");
+ *vendev = RAVEN2_VBIOS_VID_DID;
+ *rev = RAVEN2_VBIOS_REV;
+ } else {
+ printk(BIOS_NOTICE, "Using RV1/PCO VBIOS.\n");
+ *rev = PICASSO_VBIOS_REV;
+ }
+}
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h
index fd9c5fee48..e79dd87faf 100644
--- a/src/soc/amd/picasso/include/soc/cpu.h
+++ b/src/soc/amd/picasso/include/soc/cpu.h
@@ -12,4 +12,9 @@ void check_mca(void);
#define RAVEN2_A0_CPUID 0x00820f00
#define RAVEN2_A1_CPUID 0x00820f01
+#define PICASSO_VBIOS_VID_DID 0x100215d8
+#define PICASSO_VBIOS_REV 0xc1
+#define RAVEN2_VBIOS_VID_DID 0x100215dd /* VID/DID in RV2 VBIOS header */
+#define RAVEN2_VBIOS_REV 0xc4
+
#endif /* __PICASSO_CPU_H__ */