summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2021-01-14 01:40:50 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-01-24 18:15:46 +0000
commit8d0a609e6d1bfb48de781e7223f73ff979d0ce2e (patch)
treed3f40d275aeff99da11287de34bcc1bb62f7a2d6 /src
parent45b0714c89db4487074e87ada13b9886c43d9ccd (diff)
downloadcoreboot-8d0a609e6d1bfb48de781e7223f73ff979d0ce2e.tar.xz
soc,vendorcode/amd/cezanne: add basic FSP integration
This is a trimmed-down version of the Cezanne FSP integration code, so for example the UPD definitions are empty, which will be addressed later. Since coreboot just leaves the UPD values at their default, this is not a problem during the initial platform bring-up. Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/cezanne/Kconfig8
-rw-r--r--src/soc/amd/cezanne/Makefile.inc4
-rw-r--r--src/soc/amd/cezanne/fsp_params.c7
-rw-r--r--src/soc/amd/cezanne/romstage.c5
-rw-r--r--src/vendorcode/amd/fsp/cezanne/FspUpd.h22
-rw-r--r--src/vendorcode/amd/fsp/cezanne/FspmUpd.h26
-rw-r--r--src/vendorcode/amd/fsp/cezanne/FspsUpd.h23
-rw-r--r--src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h51
8 files changed, 146 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index ecdba5e6a6..15a40377cd 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -16,6 +16,7 @@ config SOC_SPECIFIC_OPTIONS
select HAVE_CF9_RESET
select IDT_IN_EVERY_STAGE
select IOAPIC
+ select PLATFORM_USES_FSP2_0
select RESET_VECTOR_IN_RAM
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
@@ -27,6 +28,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_UART
+ select UDK_2017_BINDING
config CHIPSET_DEVICETREE
string
@@ -92,6 +94,12 @@ config FSP_M_SIZE
help
Sets the size of DRAM allocation for FSP-M in linker script.
+config FSP_TEMP_RAM_SIZE
+ hex
+ default 0x40000
+ help
+ The amount of coreboot-allocated heap and stack usage by the FSP.
+
config RAMBASE
hex
default 0x10000000
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index a00a9f575c..46ac199649 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -25,11 +25,15 @@ romstage-y += romstage.c
romstage-y += uart.c
ramstage-y += chip.c
+ramstage-y += fsp_params.c
ramstage-y += gpio.c
ramstage-y += reset.c
ramstage-y += uart.c
CPPFLAGS_common += -I$(src)/soc/amd/cezanne/include
+CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/cezanne
+
+$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR)
MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR)
diff --git a/src/soc/amd/cezanne/fsp_params.c b/src/soc/amd/cezanne/fsp_params.c
new file mode 100644
index 0000000000..d3f9fcf555
--- /dev/null
+++ b/src/soc/amd/cezanne/fsp_params.c
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <fsp/api.h>
+
+void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
+{
+}
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 91074b2012..52ff0f8e41 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -1,6 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/cpu.h>
+#include <fsp/api.h>
+
+void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
+{
+}
asmlinkage void car_stage_entry(void)
{
diff --git a/src/vendorcode/amd/fsp/cezanne/FspUpd.h b/src/vendorcode/amd/fsp/cezanne/FspUpd.h
new file mode 100644
index 0000000000..c9202cea9c
--- /dev/null
+++ b/src/vendorcode/amd/fsp/cezanne/FspUpd.h
@@ -0,0 +1,22 @@
+/** @file
+ *
+ * This file is automatically generated.
+ *
+ */
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#ifdef EFI32
+# include <FspEas.h>
+# include <stdint.h>
+#else
+# include <fsp_h_c99.h>
+#endif
+
+#define FSPM_UPD_SIGNATURE 0x4d5f454e415a4543 /* 'CEZANE_M' */
+
+#define FSPS_UPD_SIGNATURE 0x535f454e415a4543 /* 'CEZANE_S' */
+
+
+#endif
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
new file mode 100644
index 0000000000..338133c33c
--- /dev/null
+++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
@@ -0,0 +1,26 @@
+/** @file
+ *
+ * This file is automatically generated.
+ *
+ */
+
+#ifndef __FSPMUPD_H__
+#define __FSPMUPD_H__
+
+#include <FspUpd.h>
+
+/** Fsp M Configuration
+**/
+typedef struct __packed {
+ uint16_t UpdTerminator;
+} FSP_M_CONFIG;
+
+/** Fsp M UPD Configuration
+**/
+typedef struct __packed {
+ /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader;
+ /** Offset 0x0020**/ FSPM_ARCH_UPD FspmArchUpd;
+ /** Offset 0x0040**/ FSP_M_CONFIG FspmConfig;
+} FSPM_UPD;
+
+#endif
diff --git a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h
new file mode 100644
index 0000000000..2b7f19c602
--- /dev/null
+++ b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h
@@ -0,0 +1,23 @@
+/** @file
+ *
+ * This file is automatically generated.
+ *
+ */
+
+#ifndef __FSPSUPD_H__
+#define __FSPSUPD_H__
+
+#include <FspUpd.h>
+
+typedef struct __packed {
+ uint16_t UpdTerminator;
+} FSP_S_CONFIG;
+
+/** Fsp S UPD Configuration
+**/
+typedef struct __packed {
+ /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader;
+ /** Offset 0x0020**/ FSP_S_CONFIG FspsConfig;
+} FSPS_UPD;
+
+#endif
diff --git a/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h b/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h
new file mode 100644
index 0000000000..c477a4ff1f
--- /dev/null
+++ b/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h
@@ -0,0 +1,51 @@
+/** @file
+ *
+ * C99 common FSP definitions from
+ * Intel Firmware Support Package External Architecture Specification v2.0
+ *
+ * These definitions come in a format that is usable outside an EFI environment.
+ **/
+#ifndef FSP_H_C99_H
+#define FSP_H_C99_H
+
+#include <stdint.h>
+
+enum {
+ FSP_STATUS_RESET_REQUIRED_COLD = 0x40000001,
+ FSP_STATUS_RESET_REQUIRED_WARM = 0x40000002,
+ FSP_STATUS_RESET_REQUIRED_3 = 0x40000003,
+ FSP_STATUS_RESET_REQUIRED_4 = 0x40000004,
+ FSP_STATUS_RESET_REQUIRED_5 = 0x40000005,
+ FSP_STATUS_RESET_REQUIRED_6 = 0x40000006,
+ FSP_STATUS_RESET_REQUIRED_7 = 0x40000007,
+ FSP_STATUS_RESET_REQUIRED_8 = 0x40000008,
+};
+
+typedef enum {
+ EnumInitPhaseAfterPciEnumeration = 0x20,
+ EnumInitPhaseReadyToBoot = 0x40,
+ EnumInitPhaseEndOfFirmware = 0xF0
+} FSP_INIT_PHASE;
+
+typedef struct __packed {
+ uint64_t Signature;
+ uint8_t Revision;
+ uint8_t Reserved[23];
+} FSP_UPD_HEADER;
+
+_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed");
+
+typedef struct __packed {
+ uint8_t Revision;
+ uint8_t Reserved[3];
+ void *NvsBufferPtr;
+ void *StackBase;
+ uint32_t StackSize;
+ uint32_t BootLoaderTolumSize;
+ uint32_t BootMode;
+ uint8_t Reserved1[8];
+} FSPM_ARCH_UPD;
+
+_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed");
+
+#endif /* FSP_H_C99_H */