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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-08-28 15:31:31 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-11-26 10:46:04 +0100
commit905507c3790829e8a6352d857bbad446e6c1c4e6 (patch)
tree76ab07397a2f93af81e9a8dda301142aa31b3b02 /src
parent4fcc9f2e54fa243a60f667b490c9f4a77261c30e (diff)
downloadcoreboot-905507c3790829e8a6352d857bbad446e6c1c4e6.tar.xz
southbridge/amd/sb700: Fix drifting system clock
Change-Id: I1698c9b9b1840d254115821f3c0e76b7211e9056 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12052 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/amd/sb700/early_setup.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index f109896ea3..f7e91207f5 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -427,10 +427,10 @@ static void sb700_devices_por_init(void)
/* Configure HPET Counter CLK period */
byte = pci_read_config8(dev, 0x43);
- byte &= 0xF7; /* unhide HPET regs */
+ byte &= 0xF7; /* Unhide HPET regs */
pci_write_config8(dev, 0x43, byte);
- pci_write_config32(dev, 0x34, 0x0429B17E ); /* Counter CLK period */
- byte |= 0x08; /* hide HPET regs */
+ pci_write_config32(dev, 0x34, 0x0429b17e); /* Counter CLK period */
+ byte |= 0x08; /* Hide HPET regs */
pci_write_config8(dev, 0x43, byte);
/* Features Enable */
@@ -661,6 +661,14 @@ static void sb700_pmio_por_init(void)
byte = pmio_read(0xbb);
byte |= 0xc0;
pmio_write(0xbb, byte);
+
+#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
+ /* Work around system clock drift issues */
+ byte = pmio_read(0xd4);
+ byte |= 0x1 << 6; /* Enable alternate 14MHz clock source */
+ byte |= 0x1 << 7; /* Disable 25MHz oscillator buffer */
+ pmio_write(0xd4, byte);
+#endif
}
/*