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authorWisley Chen <wisley.chen@quantatw.com>2017-01-14 23:19:16 +0800
committerMartin Roth <martinroth@google.com>2017-01-19 23:00:07 +0100
commit926765b11bb1beecce7d8019eaebe5737a798f0d (patch)
tree4c75431e6fdb2ca8bcbe574948dca0e66d51c65d /src
parentc0eae6112f9c5449b312d6768b618b9f7fde23c9 (diff)
downloadcoreboot-926765b11bb1beecce7d8019eaebe5737a798f0d.tar.xz
mainboard/google/snappy: Disable unused devices
The following devices i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=none BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: I9bacdbdd194ce21686c1618494d113402f2bef6c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18140 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/reef/variants/snappy/devicetree.cb10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index e46483e3b0..d420481180 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -200,15 +200,15 @@ chip soc/intel/apollolake
device i2c 0x9 on end
end
end # - I2C 5
- device pci 17.2 on end # - I2C 6
- device pci 17.3 on end # - I2C 7
+ device pci 17.2 off end # - I2C 6
+ device pci 17.3 off end # - I2C 7
device pci 18.0 on end # - UART 0
device pci 18.1 on end # - UART 1
device pci 18.2 on end # - UART 2
- device pci 18.3 on end # - UART 3
+ device pci 18.3 off end # - UART 3
device pci 19.0 on end # - SPI 0
- device pci 19.1 on end # - SPI 1
- device pci 19.2 on end # - SPI 2
+ device pci 19.1 off end # - SPI 1
+ device pci 19.2 off end # - SPI 2
device pci 1a.0 on end # - PWM
device pci 1b.0 on end # - SDCARD
device pci 1c.0 on end # - eMMC