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authorVladimir Serbinenko <phcoder@gmail.com>2016-01-31 13:21:04 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2016-02-09 22:35:23 +0100
commit93fc60621c4a2a31149f1467dfb5925cad286a60 (patch)
treea687373da33ad9d6916a1e419ec81d69c0519718 /src
parentb2eea819928090724eb54feee08e252522ac2369 (diff)
downloadcoreboot-93fc60621c4a2a31149f1467dfb5925cad286a60.tar.xz
stout: Add native gfx init
Tested during FOSDEM. Change-Id: Id095364d6e4735256e54a68ea9ae677355dd386a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13532 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/stout/Kconfig1
-rw-r--r--src/mainboard/google/stout/devicetree.cb6
2 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig
index 94229c409c..9dcde5db1f 100644
--- a/src/mainboard/google/stout/Kconfig
+++ b/src/mainboard/google/stout/Kconfig
@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_LPC_TPM
select INTEL_INT15
+ select IVYBRIDGE_LVDS
config CHROMEOS
select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 1992664944..97db8ae042 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -14,6 +14,12 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
+ # For native gfx
+ register "gfx.use_spread_spectrum_clock" = "0"
+ register "gfx.link_frequency_270_mhz" = "1"
+ register "gpu_cpu_backlight" = "0x1155"
+ register "gpu_pch_backlight" = "0x06100610"
+
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end