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authorElyes HAOUAS <ehaouas@noos.fr>2018-04-25 23:09:43 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-04-27 09:10:35 +0000
commit987f16b28ccfca6defbccad229121914ffba6767 (patch)
tree6e186e922f4b2b73a7e64ae5cd4518fef75ab18d /src
parent8b6c2e548b5690af6e5374a0d2bc62f1d4ebdbef (diff)
downloadcoreboot-987f16b28ccfca6defbccad229121914ffba6767.tar.xz
mb/pcengines/apu2/spd: Remove unneeded whitespace
Change-Id: I0c59cefa4067d3fc01b8425184e10d3caf1c81ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex9
-rw-r--r--src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex12
2 files changed, 8 insertions, 13 deletions
diff --git a/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex b/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex
index a70db53eda..835d25867e 100644
--- a/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex
+++ b/src/mainboard/pcengines/apu2/spd/HYNIX-2G-1333.spd.hex
@@ -44,7 +44,7 @@
00
# 7 Module Organization
-# bits[2:0]: 1 = 8 bits
+# bits[2:0]: 1 = 8 bits
# bits[2:0]: 2 = 16 bits
# bits[5:3]: 0 = 1 Rank
# bits[7:6]: reserved
@@ -103,7 +103,7 @@
30
# 20 Minimum Row Precharge Delay Time (tRPmin)
-# 0x6C = 13.5ns -
+# 0x6C = 13.5ns -
# 0x69 = 13.125 ns - DDR3-1333
69
@@ -190,7 +190,7 @@
86
# 42 - 47 (reserved)
-00 00 00 00 00 00
+00 00 00 00 00 00
# 48 - 55 (reserved)
00 00 00 00 00 00 00 00
@@ -212,7 +212,7 @@
# bits[4:0]: 0 = Reference Raw card A used
# bits[6:5]: 0 = revision 0
# bit7 : 0 = Reference raw cards A through AL
-# revision B4
+# revision B4
61
# 63 Address Mapping from Edge Connector to DRAM
@@ -261,4 +261,3 @@
# 126 - 127: Cyclical Redundancy Code
b6 73
-
diff --git a/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex b/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex
index ac6b4c6c9d..adc5438815 100644
--- a/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex
+++ b/src/mainboard/pcengines/apu2/spd/HYNIX-4G-1333-ECC.spd.hex
@@ -1,4 +1,4 @@
-# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix
+# HYNIX-4GBYTE-1333 The H9 N0 SPD delivered by Hynix
# SPD contents for APU 4GB DDR3 ECC (1333MHz PC1333) soldered down
# 0 Number of SPD Bytes used / Total SPD Size / CRC Coverage
@@ -102,7 +102,7 @@
30
# 20 Minimum Row Precharge Delay Time (tRPmin)
-# 0x6C = 13.5ns -
+# 0x6C = 13.5ns -
# 0x69 = 13.125 ns - DDR3-1333
69
@@ -186,7 +186,7 @@
86
# 42 - 47 (reserved)
-00 00 00 00 00 00
+00 00 00 00 00 00
# 48 - 55 (reserved)
00 00 00 00 00 00 00 00
@@ -208,7 +208,7 @@
# bits[4:0]: 0 = Reference Raw card A used
# bits[6:5]: 0 = revision 0
# bit7 : 0 = Reference raw cards A through AL
-# revision B4
+# revision B4
61
# 63 Address Mapping from Edge Connector to DRAM
@@ -255,7 +255,3 @@
# 126 - 127: Cyclical Redundancy Code
67 94
-
-
-
-