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author | Maxim Polyakov <max.senia.poliak@gmail.com> | 2019-10-08 17:33:59 +0300 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-22 12:56:20 +0000 |
commit | 9af10bf90fc6e265dcec6976b046a3d28c64f1d8 (patch) | |
tree | 88dd7026e06076bdca63eef83a967b171f7f004e /src | |
parent | 395a740bbf84629ea07e252b5f7b3d0663b72627 (diff) | |
download | coreboot-9af10bf90fc6e265dcec6976b046a3d28c64f1d8.tar.xz |
util/inteltool: Add server 5065x CPU model support
Adds the MSR table for server family 6 model 85 (5065x) processors (Sky
Lake, Cascade Lake, Cooper Lake).
The cores number for these processors exceeds the limit of 8 cores
(it is hardcoded in cpu.c). For this reason, the patch also adds code
that determines the number of processor cores at run time.
These changes are in accordance with the documentation:
[*] pages: 2-265 ... 2-286, 2-297 ... 2-308.
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
Diffstat (limited to 'src')
0 files changed, 0 insertions, 0 deletions