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authorStefan Reinauer <reinauer@chromium.org>2012-08-15 16:28:48 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-09 19:07:34 +0100
commita1ea82283d868af3681c3575722753f0789b941d (patch)
treeb78d98b3e04cd357a7fd4e0339a81dc9da3501d3 /src
parent0a1c2d62faed99edb5ffb53c2058cc6847568be0 (diff)
downloadcoreboot-a1ea82283d868af3681c3575722753f0789b941d.tar.xz
Make coreboot use the offset parameter in cbfstool create
On Sandybridge and Ivybridge systems the firmware image has to store a lot more than just coreboot, including: - a firmware descriptor - Intel Management Engine firmware - MRC cache information This option allows to limit the size of the CBFS portion in the firmware image. Change-Id: Ib87fd16fff2a6811cf898d611c966b90c939c50f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1770 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/Makefile.inc2
-rw-r--r--src/mainboard/Kconfig6
-rw-r--r--src/northbridge/intel/sandybridge/Kconfig12
3 files changed, 18 insertions, 2 deletions
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index e3fa42e0aa..868f159fee 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -65,7 +65,7 @@ prebuild-files = \
prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
$(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL)
- $(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(objcbfs)/bootblock.bin
+ $(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(objcbfs)/bootblock.bin 64 $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) ))
$(prebuild-files) true
mv $@.tmp $@
else
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index 779e061b9c..77bfa0f007 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -304,10 +304,14 @@ config ROM_SIZE
default 0x800000 if COREBOOT_ROMSIZE_KB_8192
default 0x1000000 if COREBOOT_ROMSIZE_KB_16384
-config CACHE_ROM_SIZE
+config CBFS_SIZE
hex
default ROM_SIZE
+config CACHE_ROM_SIZE
+ hex
+ default CBFS_SIZE
+
config ENABLE_POWER_BUTTON
bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL
default y if POWER_BUTTON_DEFAULT_ENABLE
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 229589998f..574a599215 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -123,4 +123,16 @@ config MRC_FILE
The path and filename of the file to use as System Agent
binary.
+config CBFS_SIZE
+ hex "Size of CBFS filesystem in ROM"
+ default 0x100000
+ help
+ On Sandybridge and Ivybridge systems the firmware image has to
+ store a lot more than just coreboot, including:
+ - a firmware descriptor
+ - Intel Management Engine firmware
+ - MRC cache information
+ This option allows to limit the size of the CBFS portion in the
+ firmware image.
+
endif