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author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-29 16:01:10 +0100 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-30 17:17:48 +0000 |
commit | a21690ba1276f94365a685fa04901e0273c426bd (patch) | |
tree | bd818b575eb51f9b03e47e487c57e62999cb6cc4 /src | |
parent | ffc87e9cbe1a811332de6a87186e9c3ad3755709 (diff) | |
download | coreboot-a21690ba1276f94365a685fa04901e0273c426bd.tar.xz |
soc/amd/stoneyridge/southbridge: replace southbridge prefix with fch
This aligns the function names with Picasso and Cezanne. Also move the
fch_* functions in the header file in the order they get called.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I49db8021edae5e537f043bf52eea1be54dc46eca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/soc/amd/stoneyridge/chip.c | 4 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 9 | ||||
-rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 4 |
3 files changed, 9 insertions, 8 deletions
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 1282f3988c..91b04c5c2c 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -118,13 +118,13 @@ static void enable_dev(struct device *dev) static void soc_init(void *chip_info) { - southbridge_init(chip_info); + fch_init(chip_info); setup_bsp_ramtop(); } static void soc_final(void *chip_info) { - southbridge_final(chip_info); + fch_final(chip_info); fam15_finalize(chip_info); } diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index f963fdfe84..72cc60a165 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -233,15 +233,16 @@ typedef struct aoac_devs { #define XHCI_FW_SIZE_OFFSET 0x8 #define XHCI_FW_BOOTRAM_SIZE 0x8000 +void bootblock_fch_early_init(void); +void bootblock_fch_init(void); +void fch_init(void *chip_info); +void fch_final(void *chip_info); + void enable_aoac_devices(void); void sb_clk_output_48Mhz(u32 osc); void sb_enable(struct device *dev); -void southbridge_final(void *chip_info); -void southbridge_init(void *chip_info); void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); -void bootblock_fch_early_init(void); -void bootblock_fch_init(void); /* * Call the mainboard to get the USB Over Current Map. The mainboard diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 11791f2b62..2a915965bb 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -402,7 +402,7 @@ static void sb_init_acpi_ports(void) PM_ACPI_TIMER_EN_EN); } -void southbridge_init(void *chip_info) +void fch_init(void *chip_info) { struct chipset_power_state *state; @@ -461,7 +461,7 @@ static void set_sb_gnvs(struct global_nvs *gnvs) & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; } -void southbridge_final(void *chip_info) +void fch_final(void *chip_info) { uint8_t restored_power = PM_S5_AT_POWER_RECOVERY; |