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authorDuncan Laurie <dlaurie@chromium.org>2013-05-28 07:54:15 -0700
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-11-24 06:28:50 +0100
commita7e9a9b75f806b290ea4fbe22a03e3489b1931f1 (patch)
treef94ba986a91a7f3792ebf8f342f369471f5a534f /src
parentd80cd2ad80b2b9debfce1fce5f94c773cb51c8cc (diff)
downloadcoreboot-a7e9a9b75f806b290ea4fbe22a03e3489b1931f1.tar.xz
slippy: Add panel power sequence timings
These are placeholder values until we can configure for the exact panel. Change-Id: Ibe88cc3588947366eb1728e5b3e1ab8c8be6dfe8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56807 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4196 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/slippy/devicetree.cb8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index 29c4763006..79fea8b89b 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -13,6 +13,14 @@ chip northbridge/intel/haswell
register "gpu_cpu_backlight" = "0x00000200"
register "gpu_pch_backlight" = "0x04000000"
+ # Enable Panel and configure power delays
+ register "gpu_panel_port_select" = "1" # eDP
+ register "gpu_panel_power_cycle_delay" = "5" # 400ms
+ register "gpu_panel_power_up_delay" = "400" # 40ms
+ register "gpu_panel_power_down_delay" = "150" # 15ms
+ register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
+ register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
+
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end