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authorAaron Durbin <adurbin@chromium.org>2016-09-16 19:25:43 -0500
committerAaron Durbin <adurbin@chromium.org>2016-09-19 17:02:52 +0200
commita9e03a34b05e00dabb63d362335d256a70cde7f8 (patch)
treee928c21ee471a4b3b4945b724245fa21f10ca6bb /src
parent79587ed8946535258112b83c4c44aab3233ba173 (diff)
downloadcoreboot-a9e03a34b05e00dabb63d362335d256a70cde7f8.tar.xz
soc/intel/apollolake: always enable BOOTBLOCK_CONSOLE
In order to ensure bootblock console output shows up in cbmem console unconditionally select BOOTBLOCK_CONSOLE. BUG=chrome-os-partner:57513 Change-Id: Ie560dd0e7102c79f6db186a11d6f934505bac116 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16622 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/apollolake/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 6eae0e13c0..3a23dbd0d2 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -12,6 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
+ select BOOTBLOCK_CONSOLE
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
# CPU specific options
@@ -128,7 +129,6 @@ config SOC_UART_DEBUG
bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE."
default n
select CONSOLE_SERIAL
- select BOOTBLOCK_CONSOLE
select DRIVERS_UART
select DRIVERS_UART_8250MEM_32
select NO_UART_ON_SUPERIO