northbridge/amd: Update all names and IDs for 00670F00

Modify the new Stoney support files to match the APU's IDs and codename.

Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit de626730758def76e558294762a06d8ec9950cb9)

Change-Id: Idc914bc80a27ac13426fdf00fc3f578ce072086f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17143
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

7 files changed, 23 insertions, 21 deletions

diff --git a/src/northbridge/amd/pi/00670F00/Kconfig b/src/northbridge/amd/pi/00670F00/Kconfig
index f5d234d3d2..e349635bae 100644
--- a/src/northbridge/amd/pi/00670F00/Kconfig
+++ b/src/northbridge/amd/pi/00670F00/Kconfig
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2015 Advanced Micro Devices, Inc.
+## Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -12,11 +12,11 @@
 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ## GNU General Public License for more details.
 ##
-config NORTHBRIDGE_AMD_PI_00660F01
+config NORTHBRIDGE_AMD_PI_00670F00
 	bool
 	select MMCONF_SUPPORT
 
-if NORTHBRIDGE_AMD_PI_00660F01
+if NORTHBRIDGE_AMD_PI_00670F00
 
 config HW_MEM_HOLE_SIZEK
 	hex
@@ -36,13 +36,13 @@ config MMCONF_BUS_NUMBER
 
 config VGA_BIOS_ID
 	string
-	default "1002,9870"
+	default "1002,98e4"
 	help
 	  The default VGA BIOS PCI vendor/device ID should be set to the
 	  result of the map_oprom_vendev() function in northbridge.c.
 
 config VGA_BIOS_FILE
 	string
-	default "3rdparty/blobs/northbridge/amd/00660F01/VBIOS.bin"
+	default "3rdparty/blobs/northbridge/amd/00670F00/VBIOS.bin"
 
 endif
diff --git a/src/northbridge/amd/pi/00670F00/chip.h b/src/northbridge/amd/pi/00670F00/chip.h
index ab0e3d20d5..917bc655ce 100644
--- a/src/northbridge/amd/pi/00670F00/chip.h
+++ b/src/northbridge/amd/pi/00670F00/chip.h
@@ -13,10 +13,10 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _PI_FAM15CZ_CHIP_H_
-#define _PI_FAM15CZ_CHIP_H_
+#ifndef _PI_FAM15ST_CHIP_H_
+#define _PI_FAM15ST_CHIP_H_
 
-struct northbridge_amd_pi_00660F01_config
+struct northbridge_amd_pi_00670F00_config
 {
 	u8 spdAddrLookup[2][2][4];
 };
diff --git a/src/northbridge/amd/pi/00670F00/dimmSpd.c b/src/northbridge/amd/pi/00670F00/dimmSpd.c
index 5c81f36f2c..e0d67d7fb6 100644
--- a/src/northbridge/amd/pi/00670F00/dimmSpd.c
+++ b/src/northbridge/amd/pi/00670F00/dimmSpd.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -28,7 +28,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA
 {
 	int spdAddress;
 	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
-	ROMSTAGE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
+	ROMSTAGE_CONST struct northbridge_amd_pi_00670F00_config *config = dev->chip_info;
 
 	if ((dev == 0) || (config == 0))
 		return AGESA_ERROR;
diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c
index 1caecf9850..ce0dde3e5c 100644
--- a/src/northbridge/amd/pi/00670F00/northbridge.c
+++ b/src/northbridge/amd/pi/00670F00/northbridge.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -582,7 +582,7 @@ static struct device_operations northbridge_operations = {
 static const struct pci_driver family15_northbridge __pci_driver = {
 	.ops	= &northbridge_operations,
 	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_15H_MODEL_006F_NB_HT,
+	.device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT,
 };
 
 static void fam15_finalize(void *chip_info)
@@ -600,7 +600,7 @@ static void fam15_finalize(void *chip_info)
 	pci_write_config32(dev, 0x60, value);
 }
 
-struct chip_operations northbridge_amd_pi_00660F01_ops = {
+struct chip_operations northbridge_amd_pi_00670F00_ops = {
 	CHIP_NAME("AMD FAM15 Northbridge")
 	.enable_dev = 0,
 	.final = fam15_finalize,
@@ -1140,8 +1140,8 @@ static void root_complex_enable_dev(struct device *dev)
 	}
 }
 
-struct chip_operations northbridge_amd_pi_00660F01_root_complex_ops = {
-	CHIP_NAME("AMD FAM16 Root Complex")
+struct chip_operations northbridge_amd_pi_00670F00_root_complex_ops = {
+	CHIP_NAME("AMD FAM15 Root Complex")
 	.enable_dev = root_complex_enable_dev,
 };
 
@@ -1152,7 +1152,7 @@ u32 map_oprom_vendev(u32 vendev)
 {
 	u32 new_vendev;
 	new_vendev =
-		((0x10029870 <= vendev) && (vendev <= 0x1002987F)) ? 0x10029870 : vendev;
+		((0x100298E0 <= vendev) && (vendev <= 0x100298EF)) ? 0x100298E0 : vendev;
 
 	if (vendev != new_vendev)
 		printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev);
diff --git a/src/northbridge/amd/pi/00670F00/northbridge.h b/src/northbridge/amd/pi/00670F00/northbridge.h
index e095f9adc9..8ac116c75d 100644
--- a/src/northbridge/amd/pi/00670F00/northbridge.h
+++ b/src/northbridge/amd/pi/00670F00/northbridge.h
@@ -13,10 +13,10 @@
  * GNU General Public License for more details.
  */
 
-#ifndef NORTHBRIDGE_AMD_AGESA_FAM16H_H
-#define NORTHBRIDGE_AMD_AGESA_FAM16H_H
+#ifndef NORTHBRIDGE_AMD_AGESA_FAM15H_H
+#define NORTHBRIDGE_AMD_AGESA_FAM15H_H
 
 static struct device_operations pci_domain_ops;
 static struct device_operations cpu_bus_ops;
 
-#endif /* NORTHBRIDGE_AMD_AGESA_FAM16H_H */
+#endif /* NORTHBRIDGE_AMD_AGESA_FAM15H_H */
diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
index cb7241634c..122b0e6d32 100644
--- a/src/northbridge/amd/pi/Kconfig
+++ b/src/northbridge/amd/pi/Kconfig
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -30,6 +30,7 @@ config S3_VGA_ROM_RUN
 
 source src/northbridge/amd/pi/00630F01/Kconfig
 source src/northbridge/amd/pi/00730F01/Kconfig
+source src/northbridge/amd/pi/00670F00/Kconfig
 source src/northbridge/amd/pi/00660F01/Kconfig
 
 config HW_MEM_HOLE_SIZEK
diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc
index 5c2d8e0443..09bc2ad729 100644
--- a/src/northbridge/amd/pi/Makefile.inc
+++ b/src/northbridge/amd/pi/Makefile.inc
@@ -1,7 +1,7 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc.
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -17,6 +17,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_PI),y)
 
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00670F00) += 00670F00
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01
 
 romstage-y += agesawrapper.c