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authorStefan Reinauer <stepan@coresystems.de>2010-06-07 08:29:36 +0000
committerStefan Reinauer <stepan@openbios.org>2010-06-07 08:29:36 +0000
commitaed992054f3af248e12ec88de4c047456fe9b104 (patch)
treef942db029eaba8e209094e75dbdd4c58e0258485 /src
parentc4f1a77cd238b106e84d15a4b62e1ffe169e6200 (diff)
downloadcoreboot-aed992054f3af248e12ec88de4c047456fe9b104.tar.xz
replace outb -> port 0x80 with post_code() in some places.
Especially most _smbus functions misuse port 0x80 writes for delays. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/cpu/amd/car/cache_as_ram.inc22
-rw-r--r--src/cpu/amd/model_lx/cache_as_ram.inc4
-rw-r--r--src/cpu/via/car/cache_as_ram.inc4
-rw-r--r--src/mainboard/digitallogic/msm586seg/romstage.c9
4 files changed, 16 insertions, 23 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 65f7555a0e..a14c9f41f5 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -49,9 +49,7 @@
/*for normal part %ebx already contain cpu_init_detected from fallback call */
cache_as_ram_setup:
-
- movb $0xA0, %al
- outb %al, $0x80
+ post_code(0xa0)
/* enable SSE */
movl %cr4, %eax
@@ -284,8 +282,7 @@ wbcache_post_fam10_setup:
orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
wrmsr
- movb $0xA1, %al
- outb %al, $0x80
+ post_code(0xa1)
/* enable cache */
movl %cr0, %eax
@@ -301,8 +298,7 @@ wbcache_post_fam10_setup:
jnc CAR_FAM10_ap
fam10_end_part1:
- movb $0xA2, %al
- outb %al, $0x80
+ post_code(0xa2)
/* Read the range with lodsl*/
cld
@@ -320,8 +316,7 @@ fam10_end_part1:
movl $(CacheBase + CacheSize - GlobalVarSize), %eax
movl %eax, %esp
- movb $0xA3, %al
- outb %al, $0x80
+ post_code(0xa3)
jmp CAR_FAM10_ap_out
CAR_FAM10_ap:
@@ -363,13 +358,11 @@ roll_cfg:
/* retrive init detected */
movl %esi, %ebx
- movb $0xA4, %al
- outb %al, $0x80
+ post_code(0xa4)
CAR_FAM10_ap_out:
- movb $0xA5, %al
- outb %al, $0x80
+ post_code(0xa5)
/* disable SSE */
movl %cr4, %eax
@@ -386,8 +379,7 @@ CAR_FAM10_ap_out:
call cache_as_ram_main
/* We will not go back */
- movb $0xAF, %al /* Should never see this postcode */
- outb %al, $0x80
+ post_code(0xaf) /* Should never see this postcode */
fixed_mtrr_msr:
.long 0x250, 0x258, 0x259
diff --git a/src/cpu/amd/model_lx/cache_as_ram.inc b/src/cpu/amd/model_lx/cache_as_ram.inc
index f776a7a727..b592bc51b9 100644
--- a/src/cpu/amd/model_lx/cache_as_ram.inc
+++ b/src/cpu/amd/model_lx/cache_as_ram.inc
@@ -169,8 +169,8 @@ leave_DCacheSetup:
popl %ecx
cmpl %ecx, %edx
je DCacheSetupGood
- movb $0xC5, %al
- outb %al, $0x80
+
+ post_code(0xc5)
DCacheSetupBad:
hlt /* issues */
jmp DCacheSetupBad
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 8bc274b381..eaa4ac9973 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -152,8 +152,8 @@ clear_fixed_var_mtrr_out:
movl %eax, %esp
#ifdef CARTEST
-testok: movb $0x40,%al
- outb %al, $0x80
+testok:
+ post_code(0x40)
xorl %edx, %edx
xorl %eax, %eax
movl $0x5c5c,%edx
diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c
index e4d9738411..c93648f60d 100644
--- a/src/mainboard/digitallogic/msm586seg/romstage.c
+++ b/src/mainboard/digitallogic/msm586seg/romstage.c
@@ -183,7 +183,7 @@ static void main(unsigned long bist)
// while(1)
print_err("STATIC MEM DONE\n");
- outb(0xee, 0x80);
+ post_code(0xee);
print_err("loop forever ...\n");
#if 0
@@ -231,13 +231,14 @@ static void main(unsigned long bist)
*dst = *src;
//print_err(" dst is now "); print_err_hex32(*dst); print_err("\n");
dst++, src++;
- outb((unsigned char)i, 0x80);
+ post_code(i & 0xff);
}
}
dumpmem();
- outb(0, 0x80);
+ post_code(0x00);
+
print_err("loop forever\n");
- outb(0xdd, 0x80);
+ post_code(0xdd);
__asm__ volatile(
"movl %0, %%edi\n\t"
"jmp *%%edi\n\t"