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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-25 12:37:33 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-09-25 12:37:33 +0000 |
| commit | b124dcf93564732100154305b8e49b2b72c6b5f6 (patch) | |
| tree | f4e279ff8e7c9d46b2d8420cc532332229977688 /src | |
| parent | 7fd931b11d6727f489f8ed76530b43a382ed3c60 (diff) | |
| download | coreboot-b124dcf93564732100154305b8e49b2b72c6b5f6.tar.xz | |
Drop <cpu/amd/mtrr.h> #include from Intel CPUs.
Three CAR implementations on Intel CPUs include <cpu/amd/mtrr.h>, which
is obviously wrong, so drop the #includes. None of their #defines are used
in the Intel code.
Build-tested with two of the affected boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/intel/model_106cx/cache_as_ram.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_6ex/cache_as_ram.inc | 1 | ||||
| -rw-r--r-- | src/cpu/intel/model_6fx/cache_as_ram.inc | 1 |
3 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 7fe66f9a6e..ab2469f11b 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -23,7 +23,6 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> /* Save the BIST result */ movl %eax, %ebp diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 414ca0711a..1f22ad0f97 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -23,7 +23,6 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> /* Save the BIST result */ movl %eax, %ebp diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 8fd37bb05c..6fc8889908 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -23,7 +23,6 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> /* Save the BIST result */ movl %eax, %ebp |