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authorArthur Heymans <arthur@aheymans.xyz>2019-11-25 23:26:36 +0100
committerNico Huber <nico.h@gmx.de>2019-12-14 15:34:08 +0000
commitb17a0f592c4d725958539a089df0f9b22ac2d7e2 (patch)
tree6485345a2c8a8c3385264d778d4e210a6124bdd9 /src
parentde640781020b10e72dd6a5cda26cab10932e94fe (diff)
downloadcoreboot-b17a0f592c4d725958539a089df0f9b22ac2d7e2.tar.xz
sb/intel/*: Remove romcc guards
These platforms now use a GCC compiled bootblock. Change-Id: I9a0139f497fe84860664195ed6584f90daecec16 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h2
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb.h2
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h2
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h2
4 files changed, 0 insertions, 8 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 127fb61cce..089d4586bf 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -90,10 +90,8 @@ struct southbridge_usb_port
int oc_pin;
};
-#ifndef __ROMCC__
void pch_enable(struct device *dev);
extern const struct southbridge_usb_port mainboard_usb_ports[14];
-#endif
void early_usb_init(const struct southbridge_usb_port *portmap);
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 77931cb20c..d35b215ab1 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -19,10 +19,8 @@
#if !defined(__ACPI__)
-#ifndef __ROMCC__
#include <device/device.h>
void i82371eb_enable(struct device *dev);
-#endif
void i82371eb_hard_reset(void);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 3d27faafad..0516a7a171 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -34,10 +34,8 @@
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
-#ifndef __ROMCC__
#include <device/device.h>
void i82801gx_enable(struct device *dev);
-#endif
void enable_smbus(void);
void i82801gx_lpc_setup(void);
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 9ee76f22f4..5785ef1a67 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -89,11 +89,9 @@ struct southbridge_usb_port {
void early_usb_init(const struct southbridge_usb_port *portmap);
-#ifndef __ROMCC__
extern const struct southbridge_usb_port mainboard_usb_ports[14];
#include <device/device.h>
void pch_enable(struct device *dev);
-#endif
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1