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authorLee Leahy <leroy.p.leahy@intel.com>2016-04-30 09:07:14 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-05-03 22:53:41 +0200
commitb1900797e3ec79845b7e380927bbb6349629165d (patch)
tree7c6ae1ef5746b69b9f27644e5ca2e1705f0d7dac /src
parent6f94c5d41a7bc8e2d7aaa32b2a50ab59f98fdc69 (diff)
downloadcoreboot-b1900797e3ec79845b7e380927bbb6349629165d.tar.xz
mainboard/intel/galileo: Enable I2C and GPIO
Enable the I2C and GPIO controllers TEST=Build and run on Galileo Gen2 Change-Id: I97bbbb7c5e72edbed14702a4129d9cfa977e1911 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14558 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/galileo/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb
index 05edffcf45..66d32a8e42 100644
--- a/src/mainboard/intel/galileo/devicetree.cb
+++ b/src/mainboard/intel/galileo/devicetree.cb
@@ -39,7 +39,7 @@ chip soc/intel/quark
device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1
device pci 15.0 on end # 8086 0935 - SPI controller 0
device pci 15.1 on end # 8086 0935 - SPI controller 1
- device pci 15.2 off end # 8086 0934 - I2C/GPIO controller
+ device pci 15.2 on end # 8086 0934 - I2C/GPIO controller
device pci 17.0 on end # 8086 11C3 - PCIe Root Port 0
device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1
device pci 1f.0 on end # 8086 095E - Legacy Bridge