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authorAngel Pons <th3fanbus@gmail.com>2020-07-03 01:02:28 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-20 17:04:46 +0000
commitb21bffae0ce5dee5d316ad544ccc6dedbc4475a1 (patch)
tree5affe6f49cf0c7b7cb5b95d6cd5dd928d624dd8b /src
parent65e5b100e2133a305ba1f471a23d75dc37a2224d (diff)
downloadcoreboot-b21bffae0ce5dee5d316ad544ccc6dedbc4475a1.tar.xz
sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASE
Make it default to 0x400, which is what the touched southbridges use. Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/asus/p8z77-m_pro/early_init.c2
-rw-r--r--src/mainboard/google/butterfly/early_init.c2
-rw-r--r--src/mainboard/google/link/early_init.c2
-rw-r--r--src/mainboard/google/parrot/early_init.c2
-rw-r--r--src/mainboard/google/stout/early_init.c2
-rw-r--r--src/mainboard/intel/dcp847ske/romstage.c2
-rw-r--r--src/mainboard/intel/emeraldlake2/early_init.c2
-rw-r--r--src/mainboard/kontron/ktqm77/early_init.c2
-rw-r--r--src/mainboard/lenovo/x220/early_init.c2
-rw-r--r--src/mainboard/roda/rv11/variants/rv11/early_init.c2
-rw-r--r--src/mainboard/roda/rv11/variants/rw11/early_init.c2
-rw-r--r--src/mainboard/samsung/lumpy/early_init.c2
-rw-r--r--src/mainboard/samsung/stumpy/early_init.c2
-rw-r--r--src/northbridge/intel/haswell/romstage.c2
-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c2
-rw-r--r--src/southbridge/intel/bd82x6x/early_smbus.c2
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h3
-rw-r--r--src/southbridge/intel/bd82x6x/smbus.c2
-rw-r--r--src/southbridge/intel/common/Kconfig5
-rw-r--r--src/southbridge/intel/i82801dx/early_smbus.c2
-rw-r--r--src/southbridge/intel/i82801dx/i82801dx.h2
-rw-r--r--src/southbridge/intel/i82801gx/early_smbus.c2
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h3
-rw-r--r--src/southbridge/intel/i82801gx/smbus.c2
-rw-r--r--src/southbridge/intel/i82801ix/early_smbus.c2
-rw-r--r--src/southbridge/intel/i82801ix/i82801ix.h2
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c2
-rw-r--r--src/southbridge/intel/i82801ix/smbus.c2
-rw-r--r--src/southbridge/intel/i82801jx/early_smbus.c2
-rw-r--r--src/southbridge/intel/i82801jx/i82801jx.h2
-rw-r--r--src/southbridge/intel/i82801jx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801jx/smbus.c2
-rw-r--r--src/southbridge/intel/ibexpeak/early_smbus.c2
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h3
-rw-r--r--src/southbridge/intel/ibexpeak/smbus.c2
-rw-r--r--src/southbridge/intel/lynxpoint/early_smbus.c2
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h3
-rw-r--r--src/southbridge/intel/lynxpoint/smbus.c2
38 files changed, 39 insertions, 44 deletions
diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c
index 87da010aa4..41db74cee9 100644
--- a/src/mainboard/asus/p8z77-m_pro/early_init.c
+++ b/src/mainboard/asus/p8z77-m_pro/early_init.c
@@ -89,7 +89,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c
index df51f66518..d00573ab7e 100644
--- a/src/mainboard/google/butterfly/early_init.c
+++ b/src/mainboard/google/butterfly/early_init.c
@@ -83,7 +83,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c
index 8360f2ac24..beda8993df 100644
--- a/src/mainboard/google/link/early_init.c
+++ b/src/mainboard/google/link/early_init.c
@@ -90,7 +90,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c
index 3c5c36369b..c8e467aee1 100644
--- a/src/mainboard/google/parrot/early_init.c
+++ b/src/mainboard/google/parrot/early_init.c
@@ -58,7 +58,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c
index e71d0eec78..93d787555f 100644
--- a/src/mainboard/google/stout/early_init.c
+++ b/src/mainboard/google/stout/early_init.c
@@ -95,7 +95,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index e81b4b66b4..c9f3dcd42f 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -18,7 +18,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c
index 119346efb7..b3802f7d9a 100644
--- a/src/mainboard/intel/emeraldlake2/early_init.c
+++ b/src/mainboard/intel/emeraldlake2/early_init.c
@@ -55,7 +55,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c
index 669577ef0d..c326795e28 100644
--- a/src/mainboard/kontron/ktqm77/early_init.c
+++ b/src/mainboard/kontron/ktqm77/early_init.c
@@ -58,7 +58,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c
index e4c854c734..c0fece9dd0 100644
--- a/src/mainboard/lenovo/x220/early_init.c
+++ b/src/mainboard/lenovo/x220/early_init.c
@@ -16,7 +16,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c
index ada4b9f1e8..4c20ee253b 100644
--- a/src/mainboard/roda/rv11/variants/rv11/early_init.c
+++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c
@@ -14,7 +14,7 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c
index f56a5e41d0..c2c9a12251 100644
--- a/src/mainboard/roda/rv11/variants/rw11/early_init.c
+++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c
@@ -44,7 +44,7 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c
index 091cbc5064..a3bf7a6742 100644
--- a/src/mainboard/samsung/lumpy/early_init.c
+++ b/src/mainboard/samsung/lumpy/early_init.c
@@ -121,7 +121,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c
index f07948291f..7e95a8b0a4 100644
--- a/src/mainboard/samsung/stumpy/early_init.c
+++ b/src/mainboard/samsung/stumpy/early_init.c
@@ -105,7 +105,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 39babf5336..5b025eba24 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -51,7 +51,7 @@ void mainboard_romstage_entry(void)
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.hpet_address = HPET_ADDR,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 1ec54b328e..e1fe7c827b 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -251,7 +251,7 @@ static void southbridge_fill_pei_data(struct pei_data *pei_data)
{
const struct device *dev = pcidev_on_root(0x19, 0);
- pei_data->smbusbar = SMBUS_IO_BASE;
+ pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE;
pei_data->wdbbar = 0x04000000;
pei_data->wdbsize = 0x1000;
pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE;
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index 7d8503bb7d..85f20a745c 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -8,7 +8,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index ed75505f65..b7842c085f 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -21,11 +21,10 @@
* It does not matter where we put the SMBus I/O base, as long as we
* keep it consistent and don't interfere with other devices. Stage2
* will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE
* again. But handling static BARs is a generic problem that should be
* solved in the device allocator.
*/
-#define SMBUS_IO_BASE 0x0400
#define SMBUS_SLAVE_ADDR 0x24
/* TODO Make sure these don't get changed by stage2 */
#define DEFAULT_GPIOBASE 0x0480
diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c
index dcd2724632..7a00cf456f 100644
--- a/src/southbridge/intel/bd82x6x/smbus.c
+++ b/src/southbridge/intel/bd82x6x/smbus.c
@@ -60,7 +60,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = SMBUS_IO_BASE;
+ res->base = CONFIG_FIXED_SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 9356a2be16..195e71579c 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -97,3 +97,8 @@ config INTEL_CHIPSET_LOCKDOWN
config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
bool
depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
+
+config FIXED_SMBUS_IO_BASE
+ hex
+ depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS
+ default 0x400
diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c
index 6649c33b8b..fc225b0466 100644
--- a/src/southbridge/intel/i82801dx/early_smbus.c
+++ b/src/southbridge/intel/i82801dx/early_smbus.c
@@ -12,7 +12,7 @@ void i82801dx_early_init(void)
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index cf852740f9..d5790ae13b 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -94,8 +94,6 @@ void aseg_smm_lock(void);
#define RTC_FAILED (1 <<2)
-#define SMBUS_IO_BASE 0x400
-
#define PM1_STS 0x00
#define WAK_STS (1 << 15)
#define PCIEXPWAK_STS (1 << 14)
diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c
index 48d9d58acc..55cb372120 100644
--- a/src/southbridge/intel/i82801gx/early_smbus.c
+++ b/src/southbridge/intel/i82801gx/early_smbus.c
@@ -7,7 +7,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index fbb6bf1868..86330f88e1 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -7,11 +7,10 @@
* It does not matter where we put the SMBus I/O base, as long as we
* keep it consistent and don't interfere with other devices. Stage2
* will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE
* again. But handling static BARs is a generic problem that should be
* solved in the device allocator.
*/
-#define SMBUS_IO_BASE 0x0400
/* TODO Make sure these don't get changed by stage2 */
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c
index e1e53c22de..6b63959d6a 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -68,7 +68,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = SMBUS_IO_BASE;
+ res->base = CONFIG_FIXED_SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c
index ba0b0c81f0..6731a02fa9 100644
--- a/src/southbridge/intel/i82801ix/early_smbus.c
+++ b/src/southbridge/intel/i82801ix/early_smbus.c
@@ -8,7 +8,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index 08b94c7056..ff94809cfb 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -80,8 +80,6 @@
#define D28Fx_SLCAP 0x54
-#define SMBUS_IO_BASE 0x0400
-
/* PCI Configuration Space (D31:F3): SMBus */
#define SMB_BASE 0x20
#define HOSTC 0x40
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 883c96428f..a2df123bc9 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -424,7 +424,7 @@ static void i82801ix_lpc_read_resources(struct device *dev)
* 0x00c0 ~ 0x00de....ISA DMA
* 0x00c1 ~ 0x00df....ISA DMA aliases
* 0x00f0.............Coprocessor Error
- * (0x0400-0x041f)....SMBus (SMBUS_IO_BASE, during raminit)
+ * (0x0400-0x041f)....SMBus (CONFIG_FIXED_SMBUS_IO_BASE, during raminit)
* 0x04d0 - 0x04d1....PIC
* 0x0500 - 0x057f....PM (DEFAULT_PMBASE)
* 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE)
diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c
index c348ed846e..815705d20a 100644
--- a/src/southbridge/intel/i82801ix/smbus.c
+++ b/src/southbridge/intel/i82801ix/smbus.c
@@ -49,7 +49,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = SMBUS_IO_BASE;
+ res->base = CONFIG_FIXED_SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c
index 55b9854598..c4b82bbf9e 100644
--- a/src/southbridge/intel/i82801jx/early_smbus.c
+++ b/src/southbridge/intel/i82801jx/early_smbus.c
@@ -7,7 +7,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index a88c19ed2f..0a353de6ff 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -83,8 +83,6 @@
#define D28Fx_SLCAP 0x54
-#define SMBUS_IO_BASE 0x0400
-
/* PCI Configuration Space (D31:F3): SMBus */
#define SMB_BASE 0x20
#define HOSTC 0x40
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index 2533d8cc72..fceeb3f80e 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -451,7 +451,7 @@ static void i82801jx_lpc_read_resources(struct device *dev)
* 0x00c0 ~ 0x00de....ISA DMA
* 0x00c1 ~ 0x00df....ISA DMA aliases
* 0x00f0.............Coprocessor Error
- * (0x0400-0x041f)....SMBus (SMBUS_IO_BASE, during raminit)
+ * (0x0400-0x041f)....SMBus (CONFIG_FIXED_SMBUS_IO_BASE, during raminit)
* 0x04d0 - 0x04d1....PIC
* 0x0500 - 0x057f....PM (DEFAULT_PMBASE)
* 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE)
diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c
index 32b64b89df..65956353da 100644
--- a/src/southbridge/intel/i82801jx/smbus.c
+++ b/src/southbridge/intel/i82801jx/smbus.c
@@ -76,7 +76,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = SMBUS_IO_BASE;
+ res->base = CONFIG_FIXED_SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c
index 7d8503bb7d..85f20a745c 100644
--- a/src/southbridge/intel/ibexpeak/early_smbus.c
+++ b/src/southbridge/intel/ibexpeak/early_smbus.c
@@ -8,7 +8,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index d0f131482b..437259ca9b 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -22,11 +22,10 @@
* It does not matter where we put the SMBus I/O base, as long as we
* keep it consistent and don't interfere with other devices. Stage2
* will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE
* again. But handling static BARs is a generic problem that should be
* solved in the device allocator.
*/
-#define SMBUS_IO_BASE 0x0400
#define SMBUS_SLAVE_ADDR 0x24
/* TODO Make sure these don't get changed by stage2 */
#define DEFAULT_GPIOBASE 0x0480
diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c
index 7e9aa57da8..01001c3bb5 100644
--- a/src/southbridge/intel/ibexpeak/smbus.c
+++ b/src/southbridge/intel/ibexpeak/smbus.c
@@ -59,7 +59,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = SMBUS_IO_BASE;
+ res->base = CONFIG_FIXED_SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c
index 7d8503bb7d..85f20a745c 100644
--- a/src/southbridge/intel/lynxpoint/early_smbus.c
+++ b/src/southbridge/intel/lynxpoint/early_smbus.c
@@ -8,7 +8,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index db3d92af26..99469448d7 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -47,11 +47,10 @@
* It does not matter where we put the SMBus I/O base, as long as we
* keep it consistent and don't interfere with other devices. Stage2
* will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE
* again. But handling static BARs is a generic problem that should be
* solved in the device allocator.
*/
-#define SMBUS_IO_BASE 0x0400
#define SMBUS_SLAVE_ADDR 0x24
#if CONFIG(INTEL_LYNXPOINT_LP)
diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c
index 39003f66a6..22bf75a4e4 100644
--- a/src/southbridge/intel/lynxpoint/smbus.c
+++ b/src/southbridge/intel/lynxpoint/smbus.c
@@ -58,7 +58,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = SMBUS_IO_BASE;
+ res->base = CONFIG_FIXED_SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |