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authorElyes HAOUAS <ehaouas@noos.fr>2016-09-29 21:39:27 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-10-01 08:35:24 +0200
commitb4d8257dffb82b0da3d64efb0a0ad4ad7b536adb (patch)
tree2fb3b96cf1945069ad2627cef2dca29b61a24029 /src
parentc3d490cc24a90c85af2897660d2765645e80b7cc (diff)
downloadcoreboot-b4d8257dffb82b0da3d64efb0a0ad4ad7b536adb.tar.xz
mainboard/jetway/j7f2: Use tabs for indents
Change-Id: Id97981a05ce4af371c765c6950ed504557b0a584 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16825 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/jetway/j7f2/devicetree.cb120
1 files changed, 60 insertions, 60 deletions
diff --git a/src/mainboard/jetway/j7f2/devicetree.cb b/src/mainboard/jetway/j7f2/devicetree.cb
index 3b99b9c3b2..ce5589f316 100644
--- a/src/mainboard/jetway/j7f2/devicetree.cb
+++ b/src/mainboard/jetway/j7f2/devicetree.cb
@@ -1,62 +1,62 @@
chip northbridge/via/cn700 # Northbridge
- device domain 0 on # PCI domain
- device pci 0.0 on end # AGP Bridge
- device pci 0.1 on end # Error Reporting
- device pci 0.2 on end # Host Bus Control
- device pci 0.3 on end # Memory Controller
- device pci 0.4 on end # Power Management
- device pci 0.7 on end # V-Link Controller
- device pci 1.0 on end # PCI Bridge
- chip southbridge/via/vt8237r # Southbridge
- # Enable both IDE channels.
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- # Both cables are 40pin.
- register "ide0_80pin_cable" = "0"
- register "ide1_80pin_cable" = "0"
- register "fn_ctrl_lo" = "0x80"
- register "fn_ctrl_hi" = "0x1d"
- device pci a.0 on end # Firewire
- device pci f.0 on end # SATA
- device pci f.1 on end # IDE
- device pci 10.0 on end # OHCI
- device pci 10.1 on end # OHCI
- device pci 10.2 on end # OHCI
- device pci 10.3 on end # OHCI
- device pci 10.4 on end # EHCI
- device pci 11.0 on # Southbridge LPC
- chip superio/fintek/f71805f # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # COM1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # COM2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.b on # HWM
- io 0x60 = 0xec00
- end
- end
- end
- device pci 11.5 on end # AC'97 audio
- # device pci 11.6 off end # AC'97 Modem
- device pci 12.0 on end # Ethernet
- end
- end
- device cpu_cluster 0 on # APIC cluster
- chip cpu/via/c7 # VIA C7
- device lapic 0 on end # APIC
- end
- end
+ device domain 0 on # PCI domain
+ device pci 0.0 on end # AGP Bridge
+ device pci 0.1 on end # Error Reporting
+ device pci 0.2 on end # Host Bus Control
+ device pci 0.3 on end # Memory Controller
+ device pci 0.4 on end # Power Management
+ device pci 0.7 on end # V-Link Controller
+ device pci 1.0 on end # PCI Bridge
+ chip southbridge/via/vt8237r # Southbridge
+ # Enable both IDE channels.
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ # Both cables are 40pin.
+ register "ide0_80pin_cable" = "0"
+ register "ide1_80pin_cable" = "0"
+ register "fn_ctrl_lo" = "0x80"
+ register "fn_ctrl_hi" = "0x1d"
+ device pci a.0 on end # Firewire
+ device pci f.0 on end # SATA
+ device pci f.1 on end # IDE
+ device pci 10.0 on end # OHCI
+ device pci 10.1 on end # OHCI
+ device pci 10.2 on end # OHCI
+ device pci 10.3 on end # OHCI
+ device pci 10.4 on end # EHCI
+ device pci 11.0 on # Southbridge LPC
+ chip superio/fintek/f71805f # Super I/O
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 on # COM2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.b on # HWM
+ io 0x60 = 0xec00
+ end
+ end
+ end
+ device pci 11.5 on end # AC'97 audio
+ # device pci 11.6 off end # AC'97 Modem
+ device pci 12.0 on end # Ethernet
+ end
+ end
+ device cpu_cluster 0 on # APIC cluster
+ chip cpu/via/c7 # VIA C7
+ device lapic 0 on end # APIC
+ end
+ end
end