gru: Add watchdog reset support

This patch adds support to reboot the whole board after a hardware
watchdog reset, to avoid the usual TPM issues. Work 100% equivalent to
Veyron.

From my tests it looks like both SRAM and PMUSRAM get preserved across
warm reboots. I'm putting the WATCHDOG_TOMBSTONE into PMUSRAM since that
makes it easier to deal with in coreboot (PMUSRAM is currently not
mapped as cached, so we don't need to worry about flushing the results
back before reboot).

BRANCH=None
BUG=chrome-os-partner:56600
TEST='stop daisydog; cat > /dev/watchdog', press CTRL+D, wait 30
seconds. Confirm that system reboots correctly without entering recovery
and we get a HW watchdog event in the eventlog.

Change-Id: I317266df40bbb221910017d1a6bdec6a1660a511
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 3b8f3d064ad56d181191c1e1c98a73196cb8d098
Original-Change-Id: I17c5a801bef200d7592a315a955234bca11cf7a3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/375562
Original-Commit-Queue: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16578
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

5 files changed, 17 insertions, 0 deletions

diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc
index 9e07a6c13a..034edde8a7 100644
--- a/src/mainboard/google/gru/Makefile.inc
+++ b/src/mainboard/google/gru/Makefile.inc
@@ -20,6 +20,7 @@ bootblock-y += chromeos.c
 bootblock-y += memlayout.ld
 bootblock-y += pwm_regulator.c
 bootblock-y += boardid.c
+bootblock-y += reset.c
 
 verstage-y += chromeos.c
 verstage-y += memlayout.ld
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index ff91e1a971..420fdf1e84 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -24,6 +24,7 @@
 #include <soc/i2c.h>
 #include <soc/pwm.h>
 #include <soc/spi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #include "board.h"
 #include "pwm_regulator.h"
@@ -75,6 +76,9 @@ void bootblock_mainboard_init(void)
 {
 	speed_up_boot_cpu();
 
+	if (rkclk_was_watchdog_reset())
+		reboot_from_watchdog();
+
 	/* Set pinmux and configure spi flashrom. */
 	write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX);
 	write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c
index 428a210e00..3eeda3863e 100644
--- a/src/soc/rockchip/rk3399/clock.c
+++ b/src/soc/rockchip/rk3399/clock.c
@@ -834,3 +834,9 @@ void rkclk_configure_emmc(void)
 			      CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
 			      (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT));
 }
+
+int rkclk_was_watchdog_reset(void)
+{
+	/* Bits 5 and 4 are "second" and "first" global watchdog reset. */
+	return read32(&cru_ptr->glb_rst_st) & 0x30;
+}
diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h
index de86ed42a9..53f16ac2a6 100644
--- a/src/soc/rockchip/rk3399/include/soc/clock.h
+++ b/src/soc/rockchip/rk3399/include/soc/clock.h
@@ -112,6 +112,7 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz);
 void rkclk_configure_tsadc(unsigned int hz);
 void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz);
 void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
+int rkclk_was_watchdog_reset(void);
 uint32_t rkclk_i2c_clock_for_bus(unsigned bus);
 
 #endif	/* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index ec12c80e5f..54cfbe1135 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -24,6 +24,11 @@ SECTIONS
 	DMA_COHERENT(0x10000000, 2M)
 	FRAMEBUFFER(0x10200000, 8M)
 
+	/* 8K of special SRAM in PMU power domain. */
+	SYMBOL(pmu_sram, 0xFF3B0000)
+	WATCHDOG_TOMBSTONE(0xFF3B1FFC, 4)
+	SYMBOL(epmu_sram, 0xFF3B2000)
+
 	SRAM_START(0xFF8C0000)
 	PRERAM_CBMEM_CONSOLE(0xFF8C0000, 7K)
 	TIMESTAMP(0xFF8C1C00, 1K)