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authorPatrick Georgi <pgeorgi@google.com>2020-04-20 09:25:51 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-04-20 08:27:32 +0000
commitb81147cb56cb7265d1584491e37accdb2f2f61d7 (patch)
tree232956042afd7bd126f9203e1d06436c5cd06b81 /src
parent85801f670de57de1e3e4785916d667a190fcb918 (diff)
downloadcoreboot-b81147cb56cb7265d1584491e37accdb2f2f61d7.tar.xz
security/vboot, mb/google: Fix build errors
There have been two cases of incompatibilities between overlapping changes, and they need to be resolved in a single commit to unbreak the tree: 1. CB:40389 introduced a new use of write_secdata while CB:40359 removed that function in favor of safe_write. Follow the refactor of the latter in the code introduced by the former. 2. CB:39849 changed google_chromeec_get_usb_pd_power_info()'s interface and adapted all its users. Except for duffy and kaisa which were only added in CB:40223 and CB:40393 respectively, so reapply the patch to puff's mainboard.c to their mainboard.c files. Change-Id: Ib8dfcd61bb79e0a487eaa60e719bd93561f2d97a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/hatch/variants/duffy/mainboard.c4
-rw-r--r--src/mainboard/google/hatch/variants/kaisa/mainboard.c4
-rw-r--r--src/security/vboot/secdata_tpm.c2
3 files changed, 7 insertions, 3 deletions
diff --git a/src/mainboard/google/hatch/variants/duffy/mainboard.c b/src/mainboard/google/hatch/variants/duffy/mainboard.c
index e8098b96ac..3f74c968b1 100644
--- a/src/mainboard/google/hatch/variants/duffy/mainboard.c
+++ b/src/mainboard/google/hatch/variants/duffy/mainboard.c
@@ -90,8 +90,9 @@ static void mainboard_set_power_limits(config_t *conf)
{
enum usb_chg_type type;
u32 watts;
+ u16 volts_mv, current_ma;
u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22
- int rv = google_chromeec_get_usb_pd_power_info(&type, &watts);
+ int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
/* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/
conf->tdp_psyspl3 = 0;
@@ -99,6 +100,7 @@ static void mainboard_set_power_limits(config_t *conf)
if (rv == 0 && type == USB_CHG_TYPE_PD) {
/* Detected USB-PD. Base on max value of adapter */
+ watts = ((u32)current_ma * volts_mv) / 1000000;
psyspl2 = watts;
conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2);
/* set max possible time window */
diff --git a/src/mainboard/google/hatch/variants/kaisa/mainboard.c b/src/mainboard/google/hatch/variants/kaisa/mainboard.c
index e8098b96ac..3f74c968b1 100644
--- a/src/mainboard/google/hatch/variants/kaisa/mainboard.c
+++ b/src/mainboard/google/hatch/variants/kaisa/mainboard.c
@@ -90,8 +90,9 @@ static void mainboard_set_power_limits(config_t *conf)
{
enum usb_chg_type type;
u32 watts;
+ u16 volts_mv, current_ma;
u32 psyspl2 = PUFF_PSYSPL2; // default barrel jack value for U22
- int rv = google_chromeec_get_usb_pd_power_info(&type, &watts);
+ int rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv);
/* use SoC default value for PsysPL3 and PL4 unless we're on USB-PD*/
conf->tdp_psyspl3 = 0;
@@ -99,6 +100,7 @@ static void mainboard_set_power_limits(config_t *conf)
if (rv == 0 && type == USB_CHG_TYPE_PD) {
/* Detected USB-PD. Base on max value of adapter */
+ watts = ((u32)current_ma * volts_mv) / 1000000;
psyspl2 = watts;
conf->tdp_psyspl3 = SET_PSYSPL2(psyspl2);
/* set max possible time window */
diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c
index 672578a481..d666ae8a5e 100644
--- a/src/security/vboot/secdata_tpm.c
+++ b/src/security/vboot/secdata_tpm.c
@@ -415,7 +415,7 @@ uint32_t antirollback_write_space_kernel(struct vb2_context *ctx)
uint8_t size = VB2_SECDATA_KERNEL_MIN_SIZE;
vb2api_secdata_kernel_check(ctx, &size);
- return write_secdata(KERNEL_NV_INDEX, ctx->secdata_kernel, size);
+ return safe_write(KERNEL_NV_INDEX, ctx->secdata_kernel, size);
}
uint32_t antirollback_read_space_rec_hash(uint8_t *data, uint32_t size)