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authorShawn Nematbakhsh <shawnn@chromium.org>2014-04-09 12:41:22 -0700
committerMarc Jones <marc.jones@se-eng.com>2014-10-28 18:08:23 +0100
commitb9590799b3aad8ef788f2c9afd7f6c2311ab169b (patch)
tree8f70b2e374eabfdf6f8b1f6b0da75101c9badc0e /src
parent1d07bf2609b506fe9782dd3fcfe544da07c9a859 (diff)
downloadcoreboot-b9590799b3aad8ef788f2c9afd7f6c2311ab169b.tar.xz
baytrail: gfx: Don't configure hotplug + backlight registers
- The hotplug register doesn't work in the way we describe. Just leave it at default. - The backlight registers will be configured by the OS driver. BUG=chrome-os-partner:27304 TEST=Manual on Rambi. Boot system in both dev and normal mode, verify that display comes up. Also verify that display functions after warm reboot and suspend / resume. BRANCH=rambi+squawks Change-Id: I5559c131f41c4a14e64e5cec66e18d3a4a46092c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/193830 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 3f287cc31e41fabef755c37361e2e65ca413c88c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7217 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/baytrail/gfx.c18
1 files changed, 0 insertions, 18 deletions
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 4ed08c93a3..9d4768f65a 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -296,9 +296,6 @@ static void gfx_panel_setup(device_t dev)
/* CONTROL */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL),
PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD),
- /* HOTPLUG */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(HOTPLUG_CTRL),
- 0x1 | (config->gpu_pipea_hotplug << 2)),
/* POWER ON */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS),
(config->gpu_pipea_port_select << 30 |
@@ -311,21 +308,12 @@ static void gfx_panel_setup(device_t dev)
/* DIVISOR */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR),
~0x1f, config->gpu_pipea_power_cycle_delay),
- /* BACKLIGHT */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL),
- (config->gpu_pipea_backlight_pwm << 16) |
- (config->gpu_pipea_backlight_pwm >> 1)),
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL2),
- BACKLIGHT_ENABLE),
REG_SCRIPT_END
};
struct reg_script gfx_pipeb_init[] = {
/* CONTROL */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL),
PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD),
- /* HOTPLUG */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(HOTPLUG_CTRL),
- 0x1 | (config->gpu_pipeb_hotplug << 2)),
/* POWER ON */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS),
(config->gpu_pipeb_port_select << 30 |
@@ -338,12 +326,6 @@ static void gfx_panel_setup(device_t dev)
/* DIVISOR */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR),
~0x1f, config->gpu_pipeb_power_cycle_delay),
- /* BACKLIGHT */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL),
- (config->gpu_pipeb_backlight_pwm << 16) |
- (config->gpu_pipeb_backlight_pwm >> 1)),
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL2),
- BACKLIGHT_ENABLE),
REG_SCRIPT_END
};