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authorKeith Short <keithshort@chromium.org>2019-05-16 14:07:43 -0600
committerDuncan Laurie <dlaurie@chromium.org>2019-05-22 16:53:19 +0000
commitbb41aba0d8c3c3cbfee44b0f7267e78fb7d012ee (patch)
tree66c4acc7abb2d19c37dbe8d470a87d64a0637631 /src
parent1835bf0fd4b77ab3eae1fb085be1667d13ed3144 (diff)
downloadcoreboot-bb41aba0d8c3c3cbfee44b0f7267e78fb7d012ee.tar.xz
post_code: add post code for invalid vendor binary
Add a new post code POST_INVALID_VENDOR_BINARY, used when coreboot fails to locate or validate a vendor supplied binary. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ib1e359d4e8772c37922b1b779135e58c73bff6b4 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/drivers/intel/fsp1_1/raminit.c14
-rw-r--r--src/drivers/intel/fsp2_0/memory_init.c6
-rw-r--r--src/drivers/intel/fsp2_0/silicon_init.c3
-rw-r--r--src/include/console/post_codes.h8
-rw-r--r--src/northbridge/intel/haswell/raminit.c3
-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c3
-rw-r--r--src/soc/intel/fsp_baytrail/romstage/romstage.c3
-rw-r--r--src/soc/intel/fsp_broadwell_de/romstage/romstage.c3
8 files changed, 30 insertions, 13 deletions
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 726cc26a0c..fc6f848089 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -195,9 +195,6 @@ void raminit(struct romstage_params *params)
}
#if CONFIG(DISPLAY_HOBS)
- if (hob_list_ptr == NULL)
- die("ERROR - HOB pointer is NULL!\n");
-
/*
* Verify that FSP is generating the required HOBs:
* 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
@@ -244,7 +241,10 @@ void raminit(struct romstage_params *params)
"ERROR - Missing one or more required FSP HOBs!\n");
/* Display the HOBs */
- print_hob_type_structure(0, hob_list_ptr);
+ if (hob_list_ptr != NULL)
+ print_hob_type_structure(0, hob_list_ptr);
+ else
+ printk(BIOS_ERR, "ERROR - HOB pointer is NULL!\n");
#endif
/* Get the address of the CBMEM region for the FSP reserved memory */
@@ -274,14 +274,16 @@ void raminit(struct romstage_params *params)
printk(BIOS_DEBUG,
"0x%08x: Chipset reserved bytes reported by FSP\n",
(unsigned int)delta_bytes);
- die("Please verify the chipset reserved size\n");
+ die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ "Please verify the chipset reserved size\n");
}
#endif
}
/* Verify the FSP 1.1 HOB interface */
if (fsp_verification_failure)
- die("ERROR - coreboot's requirements not met by FSP binary!\n");
+ die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ "ERROR - coreboot's requirements not met by FSP binary!\n");
/* Display the memory configuration */
report_memory_config();
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index b3afb98c4d..449b57d03e 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -277,7 +277,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base);
if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE)
- die("Invalid FSPM signature!\n");
+ die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ "Invalid FSPM signature!\n");
/* Copy the default values from the UPD area */
memcpy(&fspm_upd, upd, sizeof(fspm_upd));
@@ -290,7 +291,8 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
/* Fill common settings on behalf of chipset. */
if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version,
memmap) != CB_SUCCESS)
- die("FSPM_ARCH_UPD not found!\n");
+ die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ "FSPM_ARCH_UPD not found!\n");
/* Give SoC and mainboard a chance to update the UPD */
platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version);
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index 402b05d55e..b0a697d8cb 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -33,7 +33,8 @@ static void do_silicon_init(struct fsp_header *hdr)
supd = (FSPS_UPD *) (hdr->cfg_region_offset + hdr->image_base);
if (supd->FspUpdHeader.Signature != FSPS_UPD_SIGNATURE)
- die("Invalid FSPS signature\n");
+ die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ "Invalid FSPS signature\n");
upd = xmalloc(sizeof(FSPS_UPD));
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 7bd1ee0798..478c811b4d 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -333,6 +333,14 @@
#define POST_INVALID_CBFS 0xe1
/**
+ * \brief Vendor binary error
+ *
+ * Set if firmware failed to find or validate a vendor binary, or the binary
+ * generated a fatal error.
+ */
+#define POST_INVALID_VENDOR_BINARY 0xe2
+
+/**
* \brief TPM failure
*
* An error with the TPM, either unexepcted state or communications failure.
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 050dbd1ae6..c24bb67db7 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -166,7 +166,8 @@ void sdram_initialize(struct pei_data *pei_data)
default:
printk(BIOS_ERR, "MRC returned %x.\n", rv);
}
- die("Nonzero MRC return value.\n");
+ die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ "Nonzero MRC return value.\n");
}
} else {
die("UEFI PEI System Agent not found.\n");
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index f032b8aefc..e88d356593 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -235,7 +235,8 @@ void sdram_initialize(struct pei_data *pei_data)
default:
printk(BIOS_ERR, "MRC returned %x.\n", rv);
}
- die("Nonzero MRC return value.\n");
+ die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ "Nonzero MRC return value.\n");
}
} else {
die("UEFI PEI System Agent not found.\n");
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index c46b09ef97..030b5dfeed 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -208,7 +208,8 @@ void main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x48);
printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
fsp_early_init(fsp_info_header);
- die("Uh Oh! fsp_early_init should not return here.\n");
+ die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ "Uh Oh! fsp_early_init should not return here.\n");
}
/*******************************************************************************
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
index a75dabd225..121cb25d61 100644
--- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
+++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c
@@ -84,7 +84,8 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
post_code(0x48);
printk(BIOS_DEBUG, "Starting the Intel FSP (early_init)\n");
fsp_early_init(fsp_info_header);
- die("Uh Oh! fsp_early_init should not return here.\n");
+ die_with_post_code(POST_INVALID_VENDOR_BINARY,
+ "Uh Oh! fsp_early_init should not return here.\n");
}
/*******************************************************************************