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authorElyes HAOUAS <ehaouas@noos.fr>2018-04-25 15:50:27 +0200
committerMartin Roth <martinroth@google.com>2018-04-26 21:33:39 +0000
commitbc8762eaef571da9f4681d09a8ec6d2a501a8115 (patch)
tree4831a844a0a5019b951bf650599de794282a273b /src
parent570b183f7ef72dbc5d4575719cdd582c88c37d8b (diff)
downloadcoreboot-bc8762eaef571da9f4681d09a8ec6d2a501a8115.tar.xz
src: Fix a typo on "mtrr"
Change "mttrs" to mtrrs. Change-Id: I4e5930cdcba5e8f5366bb2d4ebbcb659c0c2eb27 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/drivers/intel/fsp1_1/include/fsp/romstage.h2
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c8
-rw-r--r--src/soc/intel/broadwell/include/soc/romstage.h2
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c2
-rw-r--r--src/soc/intel/broadwell/romstage/stack.c4
5 files changed, 9 insertions, 9 deletions
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index 892a653769..d79be7089c 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -54,7 +54,7 @@ struct romstage_params {
* 16. src/soc/intel/common/romstage.c/romstage_common - return
* 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return
* 18. src/soc/intel/common/romstage.c/romstage_main - return
- * 19. src/soc/intel/common/stack.c/setup_stack_and_mttrs
+ * 19. src/soc/intel/common/stack.c/setup_stack_and_mtrrs
* 20. src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup
* after call to romstage_main
* 21. FSP binary/TempRamExit
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 0e8710a903..980064c2b0 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -50,7 +50,7 @@
* Because we can't use global variables the stack is used for allocations --
* thus the need to call back and forth. */
-static void *setup_stack_and_mttrs(void);
+static void *setup_stack_and_mtrrs(void);
static void program_base_addresses(void)
{
@@ -131,7 +131,7 @@ void * asmlinkage romstage_main(unsigned long bist,
/* Call into mainboard. */
mainboard_romstage_entry(&rp);
- return setup_stack_and_mttrs();
+ return setup_stack_and_mtrrs();
}
static struct chipset_power_state power_state CAR_GLOBAL;
@@ -248,9 +248,9 @@ static inline uint32_t *stack_push(u32 *stack, u32 value)
return stack;
}
-/* setup_stack_and_mttrs() determines the stack to use after
+/* setup_stack_and_mtrrs() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
-static void *setup_stack_and_mttrs(void)
+static void *setup_stack_and_mtrrs(void)
{
int num_mtrrs;
uint32_t *slot;
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index eb4e097f00..e52004bfd5 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -33,7 +33,7 @@ asmlinkage void *romstage_main(unsigned long bist, uint32_t tsc_lo,
uint32_t tsc_high);
asmlinkage void romstage_after_car(void);
void raminit(struct pei_data *pei_data);
-void *setup_stack_and_mttrs(void);
+void *setup_stack_and_mtrrs(void);
struct chipset_power_state;
struct chipset_power_state *fill_power_state(void);
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 025855b47b..8a3f2911a0 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -80,7 +80,7 @@ asmlinkage void *romstage_main(unsigned long bist,
/* Call into mainboard. */
mainboard_romstage_entry(&rp);
- return setup_stack_and_mttrs();
+ return setup_stack_and_mtrrs();
}
/* Entry from the mainboard. */
diff --git a/src/soc/intel/broadwell/romstage/stack.c b/src/soc/intel/broadwell/romstage/stack.c
index a6a4b4bfc9..aa36e29ccf 100644
--- a/src/soc/intel/broadwell/romstage/stack.c
+++ b/src/soc/intel/broadwell/romstage/stack.c
@@ -30,9 +30,9 @@ static inline uint32_t *stack_push(u32 *stack, u32 value)
return stack;
}
-/* setup_stack_and_mttrs() determines the stack to use after
+/* setup_stack_and_mtrrs() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */
-void *setup_stack_and_mttrs(void)
+void *setup_stack_and_mtrrs(void)
{
int num_mtrrs;
uint32_t *slot;