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authorStefan Reinauer <reinauer@chromium.org>2012-10-15 13:41:56 -0700
committerRonald G. Minnich <rminnich@gmail.com>2012-11-12 17:10:52 +0100
commitbdc64c6e94bef2efbf4ec7239d1bfafc66dd8ec7 (patch)
tree307f0f0a7bb7c71c07df84da9fd2846654801f0f /src
parent9c03957b363f9206b1eacecf9911cc28ae492306 (diff)
downloadcoreboot-bdc64c6e94bef2efbf4ec7239d1bfafc66dd8ec7.tar.xz
Store timestamps before resuming from suspend
in the resume case, timestamps were collected in RAM stage but not stored in CBMEM. This leads to only a single time stamp covering 200ms being available for all of ram stage. Change-Id: Ibf0bb92caf5e032c12fe4e1b9b84b3624d499511 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1781 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/boot/hardwaremain.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 8348493048..b08fe79d0a 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -121,10 +121,6 @@ void hardwaremain(int boot_complete)
cbmemc_reinit();
#endif
#endif
-#if CONFIG_HAVE_ACPI_RESUME
- suspend_resume();
- post_code(0x8a);
-#endif
timestamp_add(TS_START_RAMSTAGE, timestamps[0]);
timestamp_add(TS_DEVICE_ENUMERATE, timestamps[1]);
@@ -132,6 +128,12 @@ void hardwaremain(int boot_complete)
timestamp_add(TS_DEVICE_ENABLE, timestamps[3]);
timestamp_add(TS_DEVICE_INITIALIZE, timestamps[4]);
timestamp_add(TS_DEVICE_DONE, timestamps[5]);
+
+#if CONFIG_HAVE_ACPI_RESUME
+ suspend_resume();
+ post_code(0x8a);
+#endif
+
timestamp_add_now(TS_CBMEM_POST);
#if CONFIG_WRITE_HIGH_TABLES