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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-09-08 13:48:36 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2013-09-21 06:21:13 +0200
commitc0beb6d4185db33eeabbceefd9004769253973a3 (patch)
treeef23f865a4f2dd3abe102891c2c2be7a25315fb2 /src
parent3d45c4077665a17735c69576638dc510f96a2dff (diff)
downloadcoreboot-c0beb6d4185db33eeabbceefd9004769253973a3.tar.xz
timestamps epia-m850: Cleanup without enabling timestamps
Remove the existing hack, platform needs a fix for EARLY_CBMEM_INIT. Change-Id: I7ce373c9698878d9fa056983e4fb571a68239c52 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3913 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/via/epia-m850/romstage.c43
-rw-r--r--src/northbridge/via/vx900/Makefile.inc1
2 files changed, 9 insertions, 35 deletions
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
index 364de4844b..23b5aeaefe 100644
--- a/src/mainboard/via/epia-m850/romstage.c
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -20,8 +20,6 @@
/*
* Inspired from the EPIA-M700
*/
-#undef CONFIG_COLLECT_TIMESTAMPS
-#define CONFIG_COLLECT_TIMESTAMPS 1
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
@@ -43,25 +41,13 @@
#define SERIAL_DEV PNP_DEV(0x4e, 0x10)
-static inline u64 tsc2u64(tsc_t tsc)
-{
- return ((u64) tsc.hi << 32) | tsc.lo;
-}
-
-/* FIXME: This board comes in two flavours. This is for the faster CPU, but
- * will probably not be correct for the other CPU */
-#define TSC_PER_USEC 1297
-static inline u32 tsc2ms(u64 end, u64 start)
-{
- return ((u32) (end - start) / TSC_PER_USEC) / 1000;
-}
-
/* cache_as_ram.inc jumps to here. */
void main(unsigned long bist)
{
u32 tolm;
- u64 start, end;
- tsc_t tsc_at_romstage_start = rdtsc();
+
+ timestamp_init(rdtsc());
+ timestamp_add_now(TS_START_ROMSTAGE);
/* First thing we need to do on the VX900, before anything else */
vx900_enable_pci_config_space();
@@ -83,13 +69,13 @@ void main(unsigned long bist)
/* Oh, almighty, give us the SMBUS */
enable_smbus();
- tsc_t tsc_before_raminit = rdtsc();
+ timestamp_add_now(TS_BEFORE_INITRAM);
/* Now we can worry about raminit.
* This board only has DDR3, so no need to worry about which DRAM type
* to use */
dimm_layout dimms = { {0x50, 0x51, SPD_END_LIST} };
vx900_init_dram_ddr3(&dimms);
- tsc_t tsc_after_raminit = rdtsc();
+ timestamp_add_now(TS_AFTER_INITRAM);
/* TODO: All these ram_checks are here to ensure we test most of the RAM
* below 4G. They should not be needed once VX900 raminit is stable */
@@ -106,25 +92,14 @@ void main(unsigned long bist)
ram_check(2048 << 20, 0x80);
print_debug("We passed RAM verify\n");
-#ifdef GONFIG_EARLY_CBMEM_INIT
+
/* We got RAM working, now we can write the timestamps to RAM */
+#if CONFIG_EARLY_CBMEM_INIT
cbmem_initialize();
- timestamp_init(tsc_at_romstage_start);
- timestamp_add(TS_START_ROMSTAGE, tsc_at_romstage_start);
- timestamp_add(TS_BEFORE_INITRAM, tsc_before_raminit);
- timestamp_add(TS_AFTER_INITRAM, tsc_after_raminit);
- timestamp_add_now(TS_END_ROMSTAGE);
#endif
+ timestamp_sync();
+ timestamp_add_now(TS_END_ROMSTAGE);
/* FIXME: See if this is needed or take this out please */
/* Disable Memcard and SDIO */
pci_mod_config8(LPC, 0x51, 0, (1 << 7) | (1 << 4));
-
- /* Informative character. Could be removed at a later time. */
- start = tsc2u64(tsc_at_romstage_start);
- end = tsc2u64(tsc_before_raminit);
- printk(BIOS_INFO, "Before raminit %ums\n", tsc2ms(end, start));
-
- start = end;
- end = tsc2u64(tsc_after_raminit);
- printk(BIOS_INFO, "Actual Raminit %ums\n", tsc2ms(end, start));
}
diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc
index 13d7de65ed..15fd859210 100644
--- a/src/northbridge/via/vx900/Makefile.inc
+++ b/src/northbridge/via/vx900/Makefile.inc
@@ -29,7 +29,6 @@ romstage-y += ./../../../southbridge/via/common/early_smbus_print_error.c
romstage-y += ./../../../southbridge/via/common/early_smbus_reset.c
romstage-y += ./../../../southbridge/via/common/early_smbus_wait_until_ready.c
romstage-y += ./../../../drivers/pc80/udelay_io.c
-romstage-$(CONFIG_COLLECT_TIMESTAMPS) += ./../../../lib/cbmem.c
ramstage-y += pci_util.c
ramstage-y += pcie.c