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authorFurquan Shaikh <furquan@google.com>2021-04-20 16:57:59 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-04-22 15:59:16 +0000
commitc1c1ba5582fa0302476491c46f18cc73b69c88ac (patch)
tree5cbb5d7b5d3bb0c4b71e1665fd8ce7bba9edfa99 /src
parent7400b612041d2b139b743b00748d5e8f8dbb8b06 (diff)
downloadcoreboot-c1c1ba5582fa0302476491c46f18cc73b69c88ac.tar.xz
soc/intel/alderlake and mb: Drop PchHdaAudioLink*Enable UPDs from chip.h
FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure GPIO pads for audio. However, mainboard is expected to perform all GPIO configration in coreboot and hence these UPDs must be set to 0. There is no need to expose these UPDs in chip.h and provide mainboard an option to set these in devicetree. This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from chip.h and the corresponding devicetree in mainboards. Currently, shadowmountain already set these UPDs to 0, whereas adlrvp set these to 1. But all the ADL boards are correctly configuring the GPIO pads for audio, so this change should not impact audio for any of these boards. BUG=b:183482000 TEST=adlrvp and shadowmountain build successfully. Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/adlrvp/devicetree.cb5
-rw-r--r--src/mainboard/intel/adlrvp/devicetree_m.cb5
-rw-r--r--src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb7
-rw-r--r--src/soc/intel/alderlake/chip.h8
-rw-r--r--src/soc/intel/alderlake/romstage/fsp_params.c17
5 files changed, 10 insertions, 32 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 4604c27928..39453d9806 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -171,11 +171,6 @@ chip soc/intel/alderlake
# HD Audio
register "PchHdaDspEnable" = "1"
- register "PchHdaAudioLinkHdaEnable" = "0"
- register "PchHdaAudioLinkDmicEnable[0]" = "1"
- register "PchHdaAudioLinkDmicEnable[1]" = "1"
- register "PchHdaAudioLinkSndwEnable[0]" = "1"
- register "PchHdaAudioLinkSndwEnable[1]" = "1"
# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
register "PchHdaIDispLinkTmode" = "2"
# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index a1edf6dd73..30aee7a7fc 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -121,11 +121,6 @@ chip soc/intel/alderlake
# HD Audio
register "PchHdaDspEnable" = "1"
- register "PchHdaAudioLinkHdaEnable" = "0"
- register "PchHdaAudioLinkDmicEnable[0]" = "1"
- register "PchHdaAudioLinkDmicEnable[1]" = "1"
- register "PchHdaAudioLinkSndwEnable[0]" = "1"
- register "PchHdaAudioLinkSndwEnable[1]" = "1"
# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
register "PchHdaIDispLinkTmode" = "3"
# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 9464f10fe0..b06e540b84 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -111,13 +111,6 @@ chip soc/intel/alderlake
# HD Audio
register "PchHdaDspEnable" = "1"
- register "PchHdaAudioLinkHdaEnable" = "0"
- register "PchHdaAudioLinkDmicEnable[0]" = "0"
- register "PchHdaAudioLinkDmicEnable[1]" = "0"
- register "PchHdaAudioLinkSspEnable[0]" = "0"
- register "PchHdaAudioLinkSspEnable[1]" = "0"
- register "PchHdaAudioLinkSndwEnable[0]" = "0"
- register "PchHdaAudioLinkSndwEnable[1]" = "0"
# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
register "PchHdaIDispLinkTmode" = "3"
# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index f1e07412b7..e0d0b6074f 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -17,10 +17,6 @@
#include <soc/usb.h>
#include <stdint.h>
-#define MAX_HD_AUDIO_DMIC_LINKS 2
-#define MAX_HD_AUDIO_SNDW_LINKS 4
-#define MAX_HD_AUDIO_SSP_LINKS 6
-
struct soc_intel_alderlake_config {
/* Common struct containing soc config data required by common code */
@@ -117,10 +113,6 @@ struct soc_intel_alderlake_config {
/* Audio related */
uint8_t PchHdaDspEnable;
- uint8_t PchHdaAudioLinkHdaEnable;
- uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS];
- uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS];
- uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS];
uint8_t PchHdaIDispLinkTmode;
uint8_t PchHdaIDispLinkFrequency;
uint8_t PchHdaIDispCodecDisconnect;
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 385246734e..74d127ea98 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -131,13 +131,16 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->PchHdaEnable = is_dev_enabled(dev);
m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
- m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
- memcpy(m_cfg->PchHdaAudioLinkDmicEnable, config->PchHdaAudioLinkDmicEnable,
- sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
- memcpy(m_cfg->PchHdaAudioLinkSspEnable, config->PchHdaAudioLinkSspEnable,
- sizeof(m_cfg->PchHdaAudioLinkSspEnable));
- memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable,
- sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
+ /*
+ * All the PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs are used by FSP only to
+ * configure GPIO pads for audio. Mainboard is expected to perform all GPIO
+ * configuration in coreboot and hence these UPDs are set to 0 to skip FSP GPIO
+ * configuration for audio pads.
+ */
+ m_cfg->PchHdaAudioLinkHdaEnable = 0;
+ memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable));
+ memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable));
+ memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
m_cfg->PchHdaIDispLinkTmode = config->PchHdaIDispLinkTmode;
m_cfg->PchHdaIDispLinkFrequency = config->PchHdaIDispLinkFrequency;
m_cfg->PchHdaIDispCodecDisconnect = config->PchHdaIDispCodecDisconnect;