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author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2017-05-16 15:36:50 +0200 |
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committer | Werner Zeh <werner.zeh@siemens.com> | 2017-05-17 21:11:57 +0200 |
commit | c7ccb6b29fb138b1d5f6ac6f702e9e378f71e2d7 (patch) | |
tree | 8b4dfd27993ea478e21a240f2d81bc60110421c0 /src | |
parent | ae10ec62391babdb8544af4e281b51f5e2515ff3 (diff) | |
download | coreboot-c7ccb6b29fb138b1d5f6ac6f702e9e378f71e2d7.tar.xz |
siemens/mc_apl1: Program eMMC DLL settings
Program eMMC DLL settings for mc_apl1 mainboard, after that system can
boot up with eMMC successfully.
Change-Id: I3d60f66ec5c7e09540ccda59f244aac6f78bf954
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/siemens/mc_apl1/devicetree.cb | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/mainboard/siemens/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/devicetree.cb index 7cb9337d44..3ad85f62ee 100644 --- a/src/mainboard/siemens/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/devicetree.cb @@ -12,6 +12,35 @@ chip soc/intel/apollolake register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 off end # - DPTF |