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authorMarshall Dawson <marshalldawson3rd@gmail.com>2018-09-26 15:52:00 -0600
committerMartin Roth <martinroth@google.com>2018-10-01 15:01:16 +0000
commitcb2b70b3d205d4352bf92e917b8f7c1e9a12a032 (patch)
tree8833a2d9718a050434521df1fe46e01e80cc17eb /src
parent9c5dc1fd449331a16b6cc50afba83e41aa20185e (diff)
downloadcoreboot-cb2b70b3d205d4352bf92e917b8f7c1e9a12a032.tar.xz
amd/stoneyridge: Add ASL helper for AOAC PwrGood Control
Add a method to assist with setting the PwrGood Control register, which will be useful for various devices. BUG=b:77602074 Change-Id: Ief602c4bc42d27b3e236d24db815b990f3a2419c Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl25
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
index b8956b4984..e875f43f40 100644
--- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl
@@ -639,3 +639,28 @@ Method(FWAK,0, Serialized) /* FCH _WAK */
}
}
}
+
+/*
+ * Helper for setting a bit in AOACxA0 PwrGood Control
+ * Arg0: bit to set or clear
+ * Arg1: 0 = clear bit[Arg0], non-zero = set bit[Arg0]
+ */
+Method(PWGC,2, Serialized)
+{
+ And (PGA3, 0xdf, Local0) /* do SwUsb3SlpShutdown below */
+ if(Arg1) {
+ Or(Arg0, Local0, Local0)
+ } else {
+ Not(Arg0, Local1)
+ And(Local1, Local0, Local0)
+ }
+ Store(Local0, PGA3)
+ if(LEqual(Arg0, 0x20)) { /* if SwUsb3SlpShutdown */
+ Store(PGA3, Local0)
+ And(Arg0, Local0, Local0)
+ while(LNot(Local0)) { /* wait SwUsb3SlpShutdown to complete */
+ Store(PGA3, Local0)
+ And(Arg0, Local0, Local0)
+ }
+ }
+}